The Engineering Projects

Master Slave JK Flip Flops in Proteus ISIS

Hey pals! I wish you are doing great. Welcome to a new lesson about the Digital Logic Circuits in The Engineering Projects. In the past tutorials, we Designed the Basic JK Flip Flop. Today, we'll talk about the following Points:

1. What are JK Flip Flops?
2. What are the Master Slave Flip Flops?
3. How does the Circuit of Master Slave Flip Flop looks?
4. How types of JK Flip Flop different from each other?
5. How does the simulation of Master JK Flip Flip take place in Proteus ISIS?

Moreover, we'll also learn some key concepts in DID YOU KNOW portions. Yet Let's recall some points about the topic.  Flip Flops are the building block of a huge number of electronic systems and devices. A Flip Flop is a Digital circuit that can take the bits as input, work with the bits, Store the bits and can output the bits. it has four basic types and at the moment we are discussing the JK Flip Flops.

DID YOU KNOW????????????

The basic JK Flip Flops face a condition where when both the Inputs are HIGH and the Clock remains HIGH for a long time, then the output of JK Flip Flop becomes uncertain and this situation is called Race around Condition in JK Flip Flops..

JK Flip Flops

As discussed in the Previous tutorial , we define the JK Flip Flops as:

"The JK Flip Flops are the Modification of Set-Reset Flip Flops that contain two outputs and are able to work with the Invalid Condition of Flip Flops."

There are mainly two types of JK Flip Flops:

1. Basic JK Flip Flops
2. Master Slave JK Flip Flops.

The main focus of this tutorial is Master JK Flip Flops so lets find what are they.

Master Slave JK Flip Flops

The Master Slave JK Flip Flops are considered better than Basic JK Flop and we define them as:

"Master Slave JK Flip Flop is two input two output sequential Logic Circuits that are the Combination of two Basic JK Flip Flops and  work well even in Race around Condition of JK Flip Flops."

In Master Slave JK Flip Flops there are two JK Flip Flops that are connected in series. The 1st JK Flip flop is called the "Master" circuit and the other is called the "Slave" circuit. The output of the Master Circuit is connected with the inputs of Slave circuits. At the same token, the output from the Slave Circuit are then fed into the input terminals of Master Circuit. The circuit also contain an Invertor that is Connected with the clock and slave circuit in such a way that the Slave circuit always contain the inverting clock signal as the master circuit. Hence when Master circuit get the clock HIGH, then the slave circuit get the LOW and vise Versa.

Difference of Basic JK Flip Flop and Master Slave JK Flip Flop

Both of the circuits belongs to the same family but they are different in many ways:

1. Basic JK Flip Flop contain only one circuit but Master Slave JK Flip Flop contains two.
2. The Basic JK Flip Flop have the Race around condition but Master Slave does not.
3. Basic JK Flip Flop is less complex than Master Slave JK Flip Flop.
4. Basic JK Flip Flop is less used than Master Slave JK Flip Flop.
5. Basic JK Flip Flop does not require any NOT Gate but Master JK Flip Flop use it.

Circuit of Master Slave JK Flip Flop

If we talk about the Circuit of the JK Flip Flop then it is always convenient to use the IC presented in Proteus ISIS. We'll show you the Circuit of Master Slave through ISIS but for the best concept and the working of the Circuit, we'll demonstrate the Logic Gate Circuit of Master Slave JK Flip Flop during the Simulation. Let's have a look at the circuit of Master Slave JK Flip Flop with IC:

DID YOU KNOW???????????

When the condition of Master Slave Flip Flop is J=1 and K=1 then the values at Q  and Q' remains change according to the flow of clock.

Working Mechanism of JK Flip Flops

It is important to understand how Master Slave Flip Flop works. When the clock Pulse is set to be high, the circuit of Slave is isolated. The Slave circuit remains isolated until the Clock is high. At this position, the J and K have an effect at the output of the whole circuit. When we set the J as LOW and S as HIGH. The output of Switch 4 (Look at the picture below) will goes to the 2nd Input of switch 6. In this Condition, the Slave circuit copies the Master circuit. Similarly, when you change the values of J and K then you will Get different outputs according to the condition of clock.

Simulation od Master Slave JK Flip Flop in Proteus ISIS

Fire up your Proteus Software.

Material Required

1. Three input NAND Gate
2. Two input NAND Gate
3. Logic Toggle
4. LED-RED
5. Ground Terminal
6. Connecting Wires

• Click the 'P" button and write NAND Gates, Logic Toggle, LED in the pop up window one after the other.
• Arrange 2 three input NAND Gates at the Working area vertically.
• Get 6 two input NAND Gate just according to the image given below:

• Set three Logic Toggles vertically, at the start of Three input NAND Gates.
• For the output device, use the Led and set them just after the last two NAND gates.
• Go to Ground Terminal from the side of Proteus screen and choose Ground Terminal.
• Set the Ground terminal just after the LEDs.
• Place the NOT Gate just below the Three inputs NAND Gates.
• Connect the whole system through wires as reported by the following picture:

NOTE: You can also use the CLOCK instead of the Logic toggles in the experiment but this was not suitable for the demonstration purpose for me.

• Change the values of the toggle J,K and CLK one after the other to check the outputs.

This is the required circuit. Truss today we saw what are the Flip Flops, what are the JK Flip Flops. We saw the types of JK Flip Flops and leaned how can we perform the Practical simulation of Master Slave JK Flip Flops.

Implementation of SR Flip Flops in Proteus

Hello Learners! welcome from the team of The Engineering Projects. We hope you are having a productive day. We are working on a series of Blogs based upon the core knowledge about Digital Logic Gates and Circuits. In this tutorial, we'll know about the SR Flip Flops and after brief introduction we will simulate SR Flip Flops in Proteus. Let's have a glimpse on the topics of today:

• What are Flip Flops?
• What are the types of Flip Flop?
• How does we design the Truth Table of SR Flip Flops?
• What are further classes of SR Flip Flips?
• Implementation of SR Flip Flops in Proteus.

Flip Flops

Flip Flops are extremely important Circuits of Digital Logic Design. We Introduce the Flip Flops as:

"Flip Flops are type of sequential Logic Circuit that contain two stable states "Zero" and "One" (because of the binary system). It is often used as Storage device and each state of Flip Flop stores one bit." 

They are the building blocks of the Electronics and play an important role in the world of Logic Circuits. Being the Binary circuits, they are essential for the computation in the computer system. The Inputs of the Flip Flops are named as "S" AND "R" that stands for Set and Reset respectively. There are two Outputs of the Flip Flop called Q and Q'. As the name suggest itself, both the outputs are the Inverse of Each Other. the Flips Flop are sequential Logic Circuits that mean they use a Clock called as "CLK"  in the circuit. the Function of clock is to synchronize the circuit. The Phenomenon in which the clock signal is change its value i.e, from 0 to 1 or from 1 to 0, is called the edge of the clock.

DID YOU KNOW?????????????????

Flip Flops are also called as Bipolar Multi-vibrator because they can store the both the Conditions of the Binary system.

When we say that Flip Flops are the Storage Devices, we mean that they does not only calculate the output from the present data, but they can also work with the data stored previously in the Flip Flops.  

Types of Flips Flops

When we talk about the types of Flip Flops, we consider mainly Four types of Flip Flops as follow:

1. SR Flip Flop
2. JK Flip Flop
3. D Flop Flops
4. K Flip Flops

These kinds are same in the composition of circuits, but the working, Construction and the results are different from each other. We'll Describe the structure of each of them along with the simulation for best concepts one after the other.

DID YOU KNOW??????????????

Flip Flops can maintain a binary state as long as there is power in the circuit, therefore can store the Data.

SR Flip Flop

The full name of SR Flip Flop is Set Reset Flip Flop. In this type of Flip Flop the Value of Output Q depends upon the Value of the "S" input. once the input of the SR Flip Flop goes high (When S and R are high) the output goes to infinity or undefined therefore this Circuit is used to  store the information.

Truth Table of SR Flip Flop

When we talk about the Truth Table of SR Latch, we find some unique behavior. The Interesting point about the SR Latch is when Set and Reset are LOW i.e, 0 then the value of the Output does not change. The circuit does not show any alternation. Moreover, when the values of inputs are HIGH, the output is undefined as discussed above. Hence the design of Truth Table of SR Flip Flop is as follow:

S	R	Q	Q’
0	0	No change	No change
0	1	0	1
1	0	1	0
1	1	Undefined	Undefined

  The SR Flip Flops are further classified into two main types:

1. Active High SR Flip Flops.
2. Active Low SR Flip Flops.

we'll learn about their details and the structure of the circuit.

Active High SR Flip Flops

The Active High SR Flip Flops are the one in which the Set input and the output terminal Q collaborate with each other. When the S is 0, the output Q is 1 and vise versa. We know that Q is always opposite to Q' hence we get the output as expected. Let's Look at the circuit of Active High SR Flip Flop and work at it in Proteus ISIS.

Active High SR Flip Flops in Proteus ISIS

• Fire Up your Proteus Software.

Material Required

1. AND Gate
2. NOR Gate
3. NAND Gate
4. Logic Toggle
5. LED-Red
6. Clock
7. Ground Terminal
8. Connecting Wires

• Click at the "P" button and Write AND Gate, NOR Gate, Logic Toggle, LED-Red, Clock one after the other and choose them through Enter button.
• Choose AND Gate from the Pick Library section and arrange two of them at the working area.
• Get two NOR Gates and arrange them just after the AND Gates.
• Get two Logic Toggles and Arrange them just before AND Gate for input.
• Choose two LEDs and fix them just after the NOR Gates.
• Ground each LED through ground Terminal Found in the Terminal modes at the left side of screen.
• Use a Clock in between AND Gates.
• Join all the components through wires just like the image given below:

Now Pop the Play button. Alter the Values of Input and observe all the outputs at each Logic Gate. You will get following Truth Table:

S	R	1	2	Q	Q’
0	0	0	0	No change	No change
0	1	0	1	0	1
1	0	1	0	1	0
1	1	Undefined	Undefined	Undefined	Undefined

DID YOU KNOW???????????

The inputs of Active Low SR Flip Flops are denoted by a a bar , a complement or a "not" word along with their name.

Active Low SR Flip Flop

The Active Low SR Flip Flops have the same output as their twin Circuit Active High SR Flip Flop. The difference is in the construction of the circuit. We use the NAND Gate in the Construction of Active Low SR Flip Flop. all other arrangements and devices are same as the previous one.

Simulation of Active Low SR Flip Flop in Proteus ISIS

• In the above Circuit of Active High SR Flip Flop, pop the left click at gate 1.
• Left click>Delete the Gate 1.
• Repeat the same step with other gates as well.
• Add the NAND gate in all the places.
• Arrange the system again as shown in the figure below:

When we Test the Active Low SR Flip Flop we get the following outputs:

S'	R'	1	2	Q	Q’
0	0	0	0	No change	No change
0	1	1	1	0	1
1	0	1	1	1	0
1	1	Undefined	Undefined	Undefined	Undefined

Hence this is another form of SR Flip Flop. Consequently, we learned about the Flip Flops, we saw what are its types , saw the subclasses of the Flip Flop and designed two types of SR Flip Flops in Proteus ISIS. Stay tuned for the other tutorial in which we'll solve the problem of undefined conditions of Flip Flops.