The Engineering Projects

Traffic Light Simulation with D Flip Flop in Proteus

Hi Mentees! we hope you are doing great. Welcome to a super easy yet useful project based upon the simulation in Proteus. We are working on the Traffic Lights project that will work with the help of D Flip Flop. In this simple tutorial, you will be aware of the following concepts:

1. What are the Traffic Lights using D Flip Flop?
2. What is the role of D Flip Flop?
3. How does the circuit of D Flip Flop work in the Traffic Lights?
4. How can you simulate the circuit of Traffic Lights with D Flip Flop in Proteus?

In addition, you will find some important information about the Traffic Lights circuit in the DID YOU KNOW Sections. Let's start learning.

Traffic Lights with D Flip Flop

Who is not aware of the traffic lights? we all observe and use the Traffic lights on the road every day. But for the sake of the concepts, let's see the traffic lights technically.

"The Traffic Lights are the signaling devices that has an electronic circuit designed to control the flow of traffic at the roads by a specialized pattern of lights."

These traffic lights are positioned at road intersections ad pedestrian crossing and other positions where the traffic flow has to maintain. The Traffic Lights depends on an array of three lights with different colors that are connected electrically The whole system is packed into a metallic structure. The LEDs turn on and off with a special pattern that depends upon the circuit. Before moving forward, refresh the concepts of Traffic Light with the logical point of view. There are three lights in the Traffic Light Signals. These are:

1. Red
2. Amber
3. Green

The red light stays last for some moments. The circuit is designed so, we get the output from the Amber color light that coordinates with the red and green light and lasts for some time. In the end, we get only Green light. All these lights are formed as a result of the sequential logic of D Flip Flop and at the end, the output of two D Flip Flops are inserted into AND Gate. The output of the Green light depends upon the AND Gate and we found the light of green LED only when the output of both the D Flip Flops are HIGH.

Role of D Flip Flop in Traffic Lights

Have you ever thought about how does the traffic light blink at a specific time? We all follow the Traffic lights but today we'll learn that what does traffic light follows. The D Flip Flops are the logical circuits and we define the D Flip Flop as:

"The D Flip Flops a dual input is Flip Flop circuit that is designed to have the input at its D Terminal, regulates the signal with the clock edge pulses and shows the output at its two output terminals."

In the Traffic Lights, we use two D Flip Flops that are responsible for the switching of the lights in on or off conditions. The D Flip Flop is the combination of the S and R Flip Flops with an inverter with one terminal. but for  simplicity, we'll use the Integrated Circuit of D Flip Flop. Hence our circuit has only four components and we get a clean, easy and useful circuit that works automatically. The input Terminals are called CLK and D terminals whereas output terminals are denoted by Q and Q'.  The Truth Table for the D Flip Flop is given next:

Inputs		Output
CLK	D	Q	Q’
0	X	No Change
1	0	0	1
1	1	1	0

The X is called the don't care condition which means in this situation, the value of D does not matters. You can learn more about D Flip Flop in https://www.theengineeringprojects.com/2021/01/d-type-flip-flop-circuit-diagrams-in-proteus.html section. The output of the D Flip Flop is connected with each LED in the Traffic lights and hence we observe the on/off situations of Traffic Lights.

Working of Traffic Lights circuit with D Flip Flop

The working of the Traffic Light starts with the change in the pulse of the clock.

1. The Q' output of the D Flip Flop 2 gives the power to the Red Light of the Traffic Light.
2. When the clock is low, there is no change in the Q' terminal of the 1st Flip Flop then the Amber light is off.
3. With the clock pulses, the Amber light of the Traffic Light turns on.
4. When the clock is high, we get the output inverse of the D Flip Flop.
5. The output Q of the D Flip Flop1 and the Q' of the D Flip Flop 2 is fed into AND Gate.
6. We know the AND Gate is HIGH only when both of its terminals are HIGH.
7.  This output of the AND Gate is connected with the Green Light of the Traffic Light.

Circuit Simulation of Traffic Lights in Proteus ISIS

For the simulation of Traffic Light in Proteus, simply follow the easy steps coming next.

Devices required for the Traffic Lights

1. D Flip Flop - DTFF
2. Traffic Lights
3. AND Gate
4. Clock pulses - DClock
5. Connecting wires

• Power up your Proteus software.
• Click the "P" button.

• Write the names of 1st three devices given above one by one and choose them.
• Get D Flip Flop twice, And Gate and Traffic Lights from the pick library and arrange them on the working area.
• Go to Generation mode(from the sidebar) >DClock and set it just on left side of the 1st D Flip Flop.

• Connect all the components with the help of connecting wires.
• Connect the Traffic Light's red light with the output of 1st D Flip Flop, the amber light with the D Flip Flop 2 and the green light with the output of AND Gate.

• Pop the play button.

Does your Traffic Lights are working well? great! if not, then check the connection again. if you face any problem then share with us. Consequently, today we learned about the logic behind the Traffic Lights. We learned that with the help of D Flip Flop, one can easily design a circuit just using four simple devices. We saw the working of the sequential on/off condition of the Traffic Lights. Stay with us for more interesting circuits.

2-bit Full Subtractor in Proteus ISIS

Hello mentees! Welcome on the behalf of The Engineering Projects. We are here with a new lesson about the Digital Logic Circuits. Logic Circuits work as heart in many electronic Circuits. The topic of today is Full Subtractor in Proteus and you will find the answers of the following questions:

1. What are 2 bit  Full Subtractors?
2. How can we design the Truth Table of 2 bit Full Subtractor?
3. How can we implement the 2 bit Full Subtractor in Proteus ISIS?

You will also learn some important chunks of information in the DID YOU KNOW sections.

2 bit Full Subtractors

A full Subtractor works really well in the processor. We’ll talk about it function but before that have a look at its definition:

• 2 bit Full Subtractor is a Combinational Logic that contain three Inputs and Two outputs and perform the function of Subtraction with two bits.
• Minuend: The 1st input is called the Minuend used to take the bit from which the 2nd value will be Subtracted.
• Subtrahend: It is called the 2nd input that is subtracted from Minuend.
• Borrow in: It is the third input that is use to take the value of the Previous borrow and we’ll denote it as B(in) here.

• Borrow Out: The Borrow out is symbolized as B(out) and it the resultant borrow that the output Terminal shows.
• Difference: This is the main result that was the concern of the experiment and its value totally depends upon the binary subtraction rules.

DID YOU KNOW?????????????????

There is another circuit called Half Subtractor that is used for the subtraction of bits but the foremost disadvantage of that circuit was its inability to work with the borrow taken in the previous calculation and the designers worked for another better Subtractors.

Truth Table of 2-bit Full Subtractor

If you know about the Concept of binary subtraction, you can use your knowledge to generate a Truth Table of 2 bit  Full Subtractor so that one can design a feasible Circuit of 2 bit Full Subtractor. The Table contain all the records that can be possible for our experiment and its result into the bargain. Thus the Truth Table for the Full Subtractor is shows as:

Minuend	Subtrahend	B(in)	Difference	B(out)
0	0	0	0	1
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Working Mechanism of 2 bit Full Subtractor

When we observe the Circuit of 2 bit Full Subtractor, we found that it is combination of two circuits of Half subtractors and the output of each circuit is then fed into an OR Gate through which we get the output of borrow. We have two types of outputs in the 2 bit  Full Subtractor:

1. Difference
2. Borrow

DID YOU KNOW?????????????????

The Full Subtractor is the one of the most fundamental Logic circuits of that are used for two bit subtraction in many computing system.

Let's have a look at the procedure of calculation of both.

Difference

The binary subtraction is similar to the decimal subtraction but it works with only two digits called 0 and 1 instead of 1 to 10 in the decimal. When we examine the answer of the bit difference while using a Truth Table in the Half Subtractor circuit, we found that it is identical to the XOR Gate. Therefore we use a XOR Gate for the Difference that is introduced as:

The type of Logic Circuit that gives the output HIGH only when both its inputs have inverse value to each other and vise versa. 

Thus the truth table for the XOR Gate is given as:

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

The output of the XOR Gate is Fed into another XOR Gate for the Full subtraction which has the connection of a Borrow Input B(in) at its Second input.

DID YOU KNOW???????????????

The Application of the  Full Subtractor is found in the ALU of computer where they are responsible for the Graphic application to decrease the difficulty in the CPU and GPU.

Borrow

Many times, the situation arrives when the Minuend<Subtrahend and in this way, the circuit need to borrow a bit from the bit presented just after it. The Full Subtractor do this through the AND Gate that contain a NOT Gate at its one end. For full Subtractor, this arrangement is again fed into the duplicated circuit and the both the outputs of this AND Gate is fed into the OR Gate that gives us the Borrow(out).

2 bit Full Subtractor in Proteus ISIS

• Start up your Proteus Software.
• Collect the following devices from the Pick Library.

Devices Required

1. XOR Gate
2. AND Gate
3. OR Gate
4. Logic Toggle
5. LED-Red

• Arrange the XOR Gate, AND Gate and NOT Gate at the working area according to the arrangement given below:

• This will form a Half Subtractor. Select the devices through a square selection area.
• Copy the whole arrangement through left click>copy to clip board.
• Paste the arrangement in the side of the circuit.
• Add an OR gate at the right side of the system. The screen should look like the image given below:

   

• Add three Logic Toggles at the left most side of the arrangement.
• Connect the Whole circuit through connecting wires by matching the circuit with the following image:
• This is the Full Subtractor circuit. Change the values of the Probes according to the Truth Table and record your observation.

  Consequently, Today we learned very useful circuit of Logic Design. We saw what are 2 bit  Full Subtractor, how can we design a  Truth Table of 2 bit Full Subtractor, what is the basic mechanism behind the working of 2 bit Full Subtractor and how can we perform a Practical implementation of 2 bit  Full Subtarctor using Proteus ISIS. In the next session, we'll learn how can we simulate a four bit Full Subtractor in Proteus ISIS and its basic concepts.

Half Subtractor in Proteus ISIS

Hey Pals! We hope you are doing Great. Today, we are going to design another application of DLD Logical Gates i.e. Half Subtractor. In our previous lectures, we covered Adders in detail, where we studied both Half Adders & Full Adders. Now its time to discuss its reciprocal i.e. Subtractors.

In this session, we'll seek the answers to the following topics:

1. What is Half Subtractor?
2. Working Principle of Half Subtractor.
3. Truth-table of Half Subtractor.
4. Simulation of Half Subtractor in Proteus using three Logic Gates.
5. Designing of Half Subtractor with NOR gate.

So, let's get started:

What is Subtractor?

The functionality of Subtractors is exactly the opposite of Adders(we discussed in previous lectures) and defined as:

• A Subtractor is a simple DLD Electronic circuit, designed using logic gates and is used to subtract binary numbers from one another.
• A DLD Subtrator generates two outputs(1-bit each) called Difference Bit and Borrow Bit.
• There are two types of Subtractors available:
• Half Subtractor. (We are discussing today)
  
• Full Subtractor. (We will discuss in the next lecture)

Now, let's have a look at the Half Subtractor:

Half Subtractor

DLD Half subtractors(same as Half Adders) are designed using logic gates and are quite simple in construction. We can define Half Subtractor as:

• "Half Subtractors are simple digital logical circuits, used to subtract two binary numbers from each other and generate two outputs called Difference Bit and Borrow Bit.
• The Half Subtractor takes two Inputs A and B and performs the subtraction operation i.e. A - B, where A is called Minuend Bit and B is called Subtrahend Bit.
  

Working Principle of Half Subtractor

The Half Subtractor has a boolean circuit. It means it works only with the two digits i.e, 0 and 1. The 0 describes the LOW bit and vise versa. It take two bits through the input Terminals and calculate the whole system then shows us the result at the Output Terminals.

Difference in Half Subtractor

The difference is obtained when we perform the minus operation with the second bit from the first bit. the calculator give us the output that is the remaining value of the 1st bit when we deduct the value of 2nd bit from it.

Borrow in Half Subtractor

In the case, when the second bit is higher then the 1st bit, the subtractor borrows a bit from the circuit. this is an essential operation because without this, subtraction can not be proceed further.

Half Subtractor Truth Table

In binary digit difference, the subtraction of 0 with 0 produces the difference 0 and the borrow 0. when the Value is change to A=0 and B=1 then the circuit borrows a bit and both the bits becomes 1 hence we get Difference=1 and borrow=1. When the inputs are A=1 and B=0 then we simply get the value Difference=1 and Borrow=0. At the same token, when A=1, B=1 then the result we get is Difference=0, Borrow=0. Using all these concepts we get the Truth Table as:

A	B	Difference	Borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

In this tutorial we'll learn to design Half subtractor in two ways:

1. Half Subtractor using three Logic Gates.
2. Half Subtractor using only NAND Gate.

DID YOU KNOW???????????

Half subtractors are used to limit the force of audio or Radio signals.

Half Subtractor Using three Logic Gates

In this type of formation we use three Logic Gate given below:

1. XOR Gate
2. NOT Gate
3. NAND Gate

When we look at the working of the Half Subtrator, we'll find that the working of the Difference mode of the Half Subtractor is same as the XOR Gate because we that that XOR Gate is the one that gives the output HIGH only when the inputs have different values from each other and vise versa. Just have a look at its Truth Table:

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

Therefore, we simple use the XOR Gat for the function of Difference. When we look at the Function of Difference. we use one AND Gate. A NOT Gate is attached with the one of the input of AND Gate. One may wonder, why we are using the two Gate when we can use the NAND Gate. but the point is, we just need the inverse condition of just one input. Therefore we use this arrangement.

Proteus simulation for Half Subtractor sing Three Gates

Material Required

1. XOR Gate
2. AND Gate
3. NOT Gate
4. LED-RED
5. Ground Terminal
6. Connecting Wires

DID YOU KNOW?????????????

Arithmatic Logic Unit uses the Half Subtractor for the functioning.

• Begin you Proteus Software.
• Choose first four Components from Pick Library through "P" Button.
•  Arrange the Logic Gates one after the other one the working area just as shown in the image:

• Arrange two Logic Toggles Just in front of the XOR Gate.
• Get one LED and Set it Just after the XOR Gate.
• Repeat the step with the with AND Gate.
• Go to Terminal Mode>Ground attach a ground Terminal with each LED.

DID YOU KNOW?????????????????

One can also use the Logic Probe to Get the output instead of LED.

• Connect all the Components through wires in accordance with the image below:

• Change the values at the Input one after the other and notice the output.

Half Subtrator using NOR Gate

Sometimes, you need to make the Circuit as simple as you can. Or you can only use one gate then it is also possible to make the whole circuit using just one gate i.e, NOR Gate. when we look at the definition, it says A NOR Gate is the one that shows the output HIGH only when the Input are LOW. So, one can use the NOR Gate in different ways just by using the connection in a specific way. Let's see how can we do this.

Proteus Simulation of Half Subtractor using NOR Gate

Material Required

1. NOR Gate
2. Logic Toggle
3. LED-RED
4. Ground Terminal
5. Connecting Wire

• Choose the Required Material.
• Arrange the NOR Gates with respect to the image given next:

 

• Set Logic Toggles in front of Gate 1.
• Attach the LED's with the output of Gate two and 5.
• Ground each LED.
• Join all the devices through Connecting wires with the help of this image:

You will Observe that this circuit works as the half subtrators when you will change the Value of Logic Toggles. Thus today we Learned what are Half Subtrator, How does the Truth table of Half Subtractor is designed, How can we design the Circuit of Half Subtractor with three Gates as well as using just a NOR Gate. If you want to learn more, you can visit the site for other tutorials as well.

T Flip Flop Circuit Diagram in Proteus ISIS

Hey Learners! I welcome you on the behalf of The Engineering Projects. I hope you are doing Great. If you are seeking for the best information about the T Flip Flop along with some small concepts and the Practical Performance, then you are at the right article. In this session you will get the following topics:

• What are T Flip Flops?
• What are the Functions of Preset and Clear Input in T Flip Flop?
• How can we Design the Truth Table of T Flip Flop?
• How can you perform the T Flip Flop simulation in very simple and useful way?

Moreover, you will also get some pieces of information in DID YOU KNOW sections. so without wasting time, lets Jump into the answer of 1st Question.

T Flip Flop

T Flip Flop belongs to the family of Flip Flops and Latches and we define the T Flip Flop as:

"T Flip Flops are bi-stable sequential Logic Circuits that are the modification of SR Flip Flops and contain just one input called T and two outputs called Q and Q' and a Clock input in the circuit. "

The Circuit is similar to the JK Flip Flop but the inputs are connected with the same Logic toggle and we control the Circuit with the help of Preset and Clear inputs. Furthermore, a Clock is used to synchronize the signals. we'll talk about this feature in upcoming sections.

DID YOU KNOW????????????????

The T Flip Flop is the modification in the JK Flip Flop that has two inputs and two outputs.

Function of Preset and Clear inputs in T Flip Flops

The Function of Preset and Clear is important. Both of these are the Synchronous Inputs. By saying this, we mean that these inputs are out of the Influence of the Clock. We change the values of these inputs, the working mechanism change according to the conditions. It seems that these inputs are not important yet they are important because one can use the circuit in different ways according to the requirements. In out Circuit and Truth Table, we denote the Preset as "P" and Clear as "C". You can Make a circuit without these inputs but it may have less functionality and working.

Working mechanism of T Flip Flop

The T Flip Flop work very similar to the JK Flip Flop but it has the difference that it can toggle with the situation of JK Flip Flop. Let's have a look at the situations in T Flip Flops.

DID YOU KNOW?????????????????

The T Flip Flops also called the Toggle Flip Flops. the toggling action is the presses in which the circuit is changed from 1 to 0 and vise versa.

When P=1 and C=0

In this condition, the Circuit is in the Set Condition. It means, the condition of Q will be same as the T . if T=1 then Q=1 and vise versa.

When P=0,C=1

This is the condition where the Circuit is in the RESET condition. The Q remains HIGH irrespective of the value of T. Toggle input have the influence on the Q'. the Output Q' follows the same condition as the T.

When P=0,C=0

In this Condition, the value of Toggle input does not have any effect on the Output, they remain open always.

When P=1,C=1

for this situation. the output is of Q is HIGH for a while then low and Q' is High.

DID YOU KNOW?????????????????

You can also use an IC for the T Flip Flop. It will be more easy and effective but it has a fixed working that is not good for the learning purpose.

T Flip Flop Truth Table

If we look at the discussion above, we'll get an idea that the T Flip Flop work according to the values of synchronous Inputs. Here's the T Flip Flop Truth Table:  

Condition	P	C	CLK	T	Q	Q’
SET	1	0	High	0	0	1
	1	0	High	1	1	1
Reset	0	1	High	0	1	0
	0	1	High	1	1	1
invalid	0	0	High	0	1	1
			High	1
Invalid	1	1	High	0	0	1
			High	1	1	1

Hence, now we have a great idea what does T Flip Flop do. Let's design the circuit of T Flip Flop in Proteus using all these concepts.

DID YOU KNOW??????????????????

When Clock is LOW, one can examine a totally different behavior of the Circuit.

T Flip Flop Circuit Diagram in Proteus ISIS

• Now we will design T Flip Flop Circuit Diagram in Proteus Software.
• Here's the components list, which will be required for this simulation:

Components Required

1. 3 input NAND Gate.
2. 2 Input NAND Gate.
3. Logic Toggle.
4. LED-red.
5. Ground Terminal.
6. Connecting Wires.

• Choose the 1st four components from the Pick Library through "P" Button one after the other.
• Set Four 3 input NAND Gate at the screen vertically just like shown in the image below:

 

• Take two Logic Toggles and set them just before the Gate 1 and one in between Gate 1 and 2 one by one.
• Take 1 logic Toggle and set it just upper side of the system.
• Repeat the step with the lower area of the Circuit.
• Get the LED and place it after the Gate Q.
• Repeat the step with the Q' Gate.
• Grab the Ground Terminal From the Terminal Mode>Ground present at the left side of screen and connect 1 with the end of LED of Q and Q'.
• Connect all the components with the help of connecting wires according to the image given below:

 

• Change the Values at the Logic toggles and observe the result.

DID YOU KNOW?????????????????

One can use the Clock Terminal present in the pick Library. But it will be difficult to understand the conditions and outputs because it is less demonstrative.

Truss, today we saw what are the T Flip Flops, How does Preset and Clear work in the T Flip Flops, how can we design the Truth Table of T Flip Flop and how can we design the whole simulation of T Flip Flop in Proteus ISIS. If you want to learn more about the circuits and simulation of Logical and Electronic Circuits, you can check our other tutorials and experiments as well.

D-Type Flip Flop Circuit Diagrams in Proteus

Hey Mentees! Welcome from the team of The Engineering Projects. We hope You are having a reproductive day. To add more reproduction, let's learn another Logical Circuit from scratch. In this Tutorial, we'll grasp the following topics:

1. What are D-Type Flip Flop?
2. Which is the IC of D Flip Flop in Proteus ISIS?
3. How is the working of D Flip Flop?
4. How can we design the Truth Table of D Flip Flop?
5. How can we Perform the formation of D Flip Flops in Proteus ISIS?

Moreover, we'll have small chunks of information in DID YOU KNOW Sections. At this instance, Let's start the learning.

D-Type Flip Flops

D-Type Flip Flops are important Logical Circuits and we Introduce it as:

"The D-Type Flip Flop is a type of Flip Flop that captures the value of D input for a specific time of the Clock edge and show the output according to the value of D at that time."

D-Type Flip Flops have the ability to Latch or delay the DATA inputs and therefore are the improved version of the SR Flip Flop (In which the data shows the Invalid output when the inputs are HIGH) . Recall that Flip Flops are the Logical Circuits that can hold and store the data in the form of bits and are important building blocks of many of electronic devices and circuits.

DID YOU KNOW???????????????????????? The D Flip Flop is also known as the Data Flip Flop.

When we observe the circuit of D Flip Flop we observe 2 Important points in the D flip Flops:

1. The D Flip Flop is the circuit of active High SR Flip Flop that have the S and R inputs connected together with an invertor gate so that both S  and R (looking with the point of view of SR Flip Flop) will always have the opposite state to each other.
2. The circuit has only one input called D input and it always has a clock that has one of the major effect at the output of D Flip Flop.

D Flip Flop IC

IC's play a magical role in the world of electronics. They make the circuit so simple and decrease the chances of the errors in the circuit. for D Flip Flop, the IC Used has a number CD4013 and for better understanding, D Flip Flop IC named 4013 is shown in the Proteus software in the image below: The S and R are the additional pins to use it for the higher level Experiments. Yet for the simplicity and core information, we'll use Logic Gates when we'll perform in the practical section.

Working of D Flip Flop

In the working of D type Flip Flop, we observe that the D is the only input of the D Flip Flop. yet, the Clock also has the effect in the output of the circuit. Due to the Latched Circuit of Flip Flops, all this discussion would be pointless if we took the concept in the mind that at every pulse, the data of the Flip Flop is changed. Truss, we use an Enabler or Clock in the Circuit through which we can separate the circuit from the input at the instance of our will. When clock is HIGH: Thus, when the D is set HIGH the circuit is said to be in the "Set" State. By the same token, when the D input is LOW the circuit is said to be in the "Reset" position. Unlike SR Flip Flop, the output Q is same as the value of D input and Q' is the vise versa. When Clock is LOW: During the operation when the Clock or Enable input is LOW, any value at the D does not have any effect on the circuit's output. This position is called the "Don't Care" State of D Flip Flop.

Truth Table of D Flip Flop

Based upon the Concepts given above, one can easily design the Truth Table of the D Flip Flop. Let's have a look at the Truth Table.

Inputs		Output
CLK	D	Q	Q’
0	X	No Change
1	0	0	1
1	1	1	0

For the purpose of best understanding, we are going to check these concepts and the circuit information in the simulation Software. We are using the Proteus ISIS here.

Performance of D Flip Flop i Proteus ISIS

To perform the experiment in the software, just follow the simple steps given next.

Material Required

1. NAND Gate
2. NOT Gate
3. Logic Toggle
4. LED-RED
5. Ground Terminal
6. Connecting wires

• Fire up your Proteus ISIS.
• Pop the "P" button present at the screen and Write the name of 1st four devices and select them one after the other.
• Arrange four NAND gates and the inverter gate (NOT Gate) at the working area just according to the image given below:

• Take Logic Toggles and arrange them just at the left side of the system.
• Get the LED's for the output and connect one of them with the output of switch Q and Q'.
• Go to Terminal mode>Ground, attach the one ground Terminal with each the LEDs.
• Connect all the devices according to the diagram given next:

• Change the value of the Clock and observe does the value of the output change?
• Turning the LED on means the output is HIGH and vise versa.
• For convenience, the D Flip Flop can also be obtained by using a NAND as NOT in the Circuit as shown in figure:

DID YOU KNOW?????????????

In real life, the Clock is used in the place of Logic Gate (as shown in the image above) because it automatically changes the direction and change the output of the D Flip Flop. 

NOTE: You can also use the Logic Probe instead of the Grounded LED. Truss, in this session, we saw what are the D Flip Flops, how does they work, how an we design the Truth Table of D Flip Flop and how can we perform it practically in Proteus ISIS. In the next session, we'll know what are T Flip Flop and how is its Simulation in Proteus ISIS.

2-to-1 Multiplexer using Logic Gates in Proteus ISIS

Hi Mentees! I welcome you on behalf of The Engineering Projects. In this section of this DLD Logic gates series, we are discussing different applications of logic gates. We have discussed DLD Adders and Subtractors in our previous lectures and now it's time to have a look at DLD Multiplexers.

1. What are Multiplexers?
2. What are the types of Multiplexers?
3. What are the two input Multiplexers?
4. How can we simulate the Circuit of 2 to 2 MUX in Proteus ISIS?
5. How can we use the 2 to 1 MUX as OR, AND and NOT gates?

What are Multiplexers?

When I heard the word Multiplexer, I thought that as Adder adds numbers, Subtractor subtracts numbers, similarly, the Multiplexer will multiply binary numbers but that's not the case. Multiplexer is defined as:

• A Multiplexer(also called MUX or MPX) is a simple digital electronic circuit, designed using DLD Logic Gates and is used to select a single input from multiple inputs provided to it.
• The input selection is controlled by a separate Input called Select Input(S).
• The selected Input is then forwarded to the Output Terminal.
• In a simple two Input(A₁, A₂) MUX,
1. If S = 0, the output(Y) will be A₁
2. If S = 1, the output(Y) will be A₂.

A Multiplexer is also called Data Selector, Universal Logic Selector, Many-to-one Logic converter and Parallel-to-Serial Convertor because it has the ability to select a single input from multiple inputs.

Let's understand the working principle of Multiplexer in detail:

Multiplexer Working Principle

Let's take the example of the simplest multiplexer i.e. 2-to-1 MUX. It has 2 normal inputs(A₁ , A₂ ) and 1 Select Input(S) and it generates single Output(Y). Here's the block diagram of a simple 2-to-1 Multiplexer:

As discussed above, the selection of inputs is controlled by the Select Pin(S). So, if S = 0, the output will be A₁ and if S = 1, the output will be A₂. The relation between Select Input and Output is shown in the below truth table:

Select Input(S)	Output(Y)
0	A1
1	A2

We can understand from the above truth table that we can control maximum 2 inputs from a single Select Input. So, in order to control more than 2 inputs, we need to increase the number of Select Inputs. For example, 2 Select Inputs can control a maximum of 4 Normal Inputs. So, the relation between Select and Normal Inputs can be described by the following formula:

Normal Inputs = 2ⁿ

where, n represents the Select Inputs.

So, if we have 5 Select Inputs, we can easily control 2⁵ = 32 Normal Inputs.

We have discussed its types in our Lecture. 2-to-1 Multiplexer As the name justifies, the 2 to 1 Multiplexer is the one where we have two inputs and only one output. Let's find what are 2:1 MUX. " The kind of Multiplexer or MUX that contains two inputs, one Selector and one Output is called 2-to-1 MUX or multiplexer. The inputs are usually named as D0 and D1, the selector is termed as S and the output is called Y." You can change the names of the inputs and output according to your choice.

Truth Table of 2-to-1 MUX

As we have discussed earlier, the inputs of Multiplexer depends upon a Selector S. therefore, when we design a Truth Table, we include a Selector also in it. While designing a 2-to-1 MUX, we follow the expression given below:

Y=D0S' + D1S

Considering the expression above we get the Truth Table of 2-to-1 Multiplexer as follow:

S	D0	D1	Y
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	0
1	0	1	1
1	1	0	1
1	1	1	1

  On the basis of above discussion, I am going to Produce a 2-into-1 MUX in Proteus ISIS.

Implementing 2-to-1 Multiplexer in Proteus ISIS

To Design a 2-to-1 Multiplexer, we need the following material:

Material Required

1. AND Gate
2. OR Gate
3. NOT Gate
4. Logic Toggle
5. LED
6. Ground Terminal

• Grab the required Material from the Pick Library one after the other by Pressing a "P" button present at the screen.
• Hit and hold the Name of the chosen Logic Gates one by one and arrange them at the screen according to the given image:

• Get Three Logic Toggles and set them just before the Logic Gates.
• Arrange an LED below the OR Gate's output.
• To have a ground Terminal, left click the mouse >Go to Place>Terminal>Ground.
• Join all the Components according to given image below:

• Pop the Play button just at the left corner of the screen and change the input.

NOTE: If your circuit shows the error of duplication, Simply change the names of gate by double clicking them and give them the desired name.

• Change the conditions of the System by changing the values of inputs and observe the output.

One can Use the 2-into-1 Multiplexer as the other Logic Gates. We discuss the usage of 2-into-1 MUX for the following Gates:

1. AND Gate
2. OR Gate
3. NOT Gate

Let's have a detailed way to use the 2-to-1 Multiplexer in the following way.

Implementing OR Gate through 2-to-1 Multiplexer in Proteus ISIS

The MUX Can easily be used to implement Basic Logic Gate. But before that Recall that what is an OR Gate.

"An OR Gate is a two input Logical Gate that give the output LOW only when both the outputs are LOW."

Procedure for the conversion of 2-to-1 Multiplexer into OR Gate

• Fix the value of D0 to 1 all the time.
• Change the Value of the S and D2 according to the Truth Table given below and match the result.

S	D0	D1	Y
0	0	0	0
0	0	1	1
1	0	0	1
1	0	1	1

Notice that the value of output is equals to the AND Gate.

Implementing AND Gate through 2-to-1 MUX in Proteus ISIS

Recall the definition of AND Gate:

" The AND Gate is the one that consist of two inputs and gives the input HIGH only when both the Inputs are HIGH."

Follow the simple steps to use 2-to 1 MUX as an AND Gate.

Steps to use 2-into-1 MUX as AND Gate

• Set the value of D0 as 1.
• Change the values of S and D0 according to table and record your observations.

 

S	D0	D1	Y
0	0	0	0
0	1	0	0
1	0	0	0
1	1	0	1

You can clearly see that the output is same as the AND Gate hence, you can use it as AND Gate.

NOT Gate through 2 to 1 MUX

Prior to start, Let's refresh the definition of NOT Gate in our minds:

"The NOT Gate is a 1 input invertor Logic Gate that gives the output 1 when input is zero and vice versa."

To use the 2 to 1 MUX as NOT Gate, just follow the steps:

• Set the D0 input as 0.
• Set D1 as 1.
• Change the value of S as 1 and zero  one after the other.
• You will Observe that when S=1 the output is 0 and vice versa.
• Hence this is our required result.

You can check our website for the XNOR, XOR and NOR Gate from 2 to 1 MUX in our Tutorials. Consequently, today we leaned interesting Circuits. We saw what are 2 to 1 Multiplexers. We made a circuit of the 2 to 1 MUX and from the circuit, we found how can we use them as OR, AND and NOT logic Gates along with the truth tables of each.

Master Slave JK Flip Flops in Proteus ISIS

Hey pals! I wish you are doing great. Welcome to a new lesson about the Digital Logic Circuits in The Engineering Projects. In the past tutorials, we Designed the Basic JK Flip Flop. Today, we'll talk about the following Points:

1. What are JK Flip Flops?
2. What are the Master Slave Flip Flops?
3. How does the Circuit of Master Slave Flip Flop looks?
4. How types of JK Flip Flop different from each other?
5. How does the simulation of Master JK Flip Flip take place in Proteus ISIS?

Moreover, we'll also learn some key concepts in DID YOU KNOW portions. Yet Let's recall some points about the topic.  Flip Flops are the building block of a huge number of electronic systems and devices. A Flip Flop is a Digital circuit that can take the bits as input, work with the bits, Store the bits and can output the bits. it has four basic types and at the moment we are discussing the JK Flip Flops.

DID YOU KNOW????????????

The basic JK Flip Flops face a condition where when both the Inputs are HIGH and the Clock remains HIGH for a long time, then the output of JK Flip Flop becomes uncertain and this situation is called Race around Condition in JK Flip Flops..

JK Flip Flops

As discussed in the Previous tutorial , we define the JK Flip Flops as:

"The JK Flip Flops are the Modification of Set-Reset Flip Flops that contain two outputs and are able to work with the Invalid Condition of Flip Flops."

There are mainly two types of JK Flip Flops:

1. Basic JK Flip Flops
2. Master Slave JK Flip Flops.

The main focus of this tutorial is Master JK Flip Flops so lets find what are they.

Master Slave JK Flip Flops

The Master Slave JK Flip Flops are considered better than Basic JK Flop and we define them as:

"Master Slave JK Flip Flop is two input two output sequential Logic Circuits that are the Combination of two Basic JK Flip Flops and  work well even in Race around Condition of JK Flip Flops."

In Master Slave JK Flip Flops there are two JK Flip Flops that are connected in series. The 1st JK Flip flop is called the "Master" circuit and the other is called the "Slave" circuit. The output of the Master Circuit is connected with the inputs of Slave circuits. At the same token, the output from the Slave Circuit are then fed into the input terminals of Master Circuit. The circuit also contain an Invertor that is Connected with the clock and slave circuit in such a way that the Slave circuit always contain the inverting clock signal as the master circuit. Hence when Master circuit get the clock HIGH, then the slave circuit get the LOW and vise Versa.

Difference of Basic JK Flip Flop and Master Slave JK Flip Flop

Both of the circuits belongs to the same family but they are different in many ways:

1. Basic JK Flip Flop contain only one circuit but Master Slave JK Flip Flop contains two.
2. The Basic JK Flip Flop have the Race around condition but Master Slave does not.
3. Basic JK Flip Flop is less complex than Master Slave JK Flip Flop.
4. Basic JK Flip Flop is less used than Master Slave JK Flip Flop.
5. Basic JK Flip Flop does not require any NOT Gate but Master JK Flip Flop use it.

Circuit of Master Slave JK Flip Flop

If we talk about the Circuit of the JK Flip Flop then it is always convenient to use the IC presented in Proteus ISIS. We'll show you the Circuit of Master Slave through ISIS but for the best concept and the working of the Circuit, we'll demonstrate the Logic Gate Circuit of Master Slave JK Flip Flop during the Simulation. Let's have a look at the circuit of Master Slave JK Flip Flop with IC:

DID YOU KNOW???????????

When the condition of Master Slave Flip Flop is J=1 and K=1 then the values at Q  and Q' remains change according to the flow of clock.

Working Mechanism of JK Flip Flops

It is important to understand how Master Slave Flip Flop works. When the clock Pulse is set to be high, the circuit of Slave is isolated. The Slave circuit remains isolated until the Clock is high. At this position, the J and K have an effect at the output of the whole circuit. When we set the J as LOW and S as HIGH. The output of Switch 4 (Look at the picture below) will goes to the 2nd Input of switch 6. In this Condition, the Slave circuit copies the Master circuit. Similarly, when you change the values of J and K then you will Get different outputs according to the condition of clock.

Simulation od Master Slave JK Flip Flop in Proteus ISIS

Fire up your Proteus Software.

Material Required

1. Three input NAND Gate
2. Two input NAND Gate
3. Logic Toggle
4. LED-RED
5. Ground Terminal
6. Connecting Wires

• Click the 'P" button and write NAND Gates, Logic Toggle, LED in the pop up window one after the other.
• Arrange 2 three input NAND Gates at the Working area vertically.
• Get 6 two input NAND Gate just according to the image given below:

• Set three Logic Toggles vertically, at the start of Three input NAND Gates.
• For the output device, use the Led and set them just after the last two NAND gates.
• Go to Ground Terminal from the side of Proteus screen and choose Ground Terminal.
• Set the Ground terminal just after the LEDs.
• Place the NOT Gate just below the Three inputs NAND Gates.
• Connect the whole system through wires as reported by the following picture:

NOTE: You can also use the CLOCK instead of the Logic toggles in the experiment but this was not suitable for the demonstration purpose for me.

• Change the values of the toggle J,K and CLK one after the other to check the outputs.

This is the required circuit. Truss today we saw what are the Flip Flops, what are the JK Flip Flops. We saw the types of JK Flip Flops and leaned how can we perform the Practical simulation of Master Slave JK Flip Flops.

Implementation of SR Flip Flops in Proteus

Hello Learners! welcome from the team of The Engineering Projects. We hope you are having a productive day. We are working on a series of Blogs based upon the core knowledge about Digital Logic Gates and Circuits. In this tutorial, we'll know about the SR Flip Flops and after brief introduction we will simulate SR Flip Flops in Proteus. Let's have a glimpse on the topics of today:

• What are Flip Flops?
• What are the types of Flip Flop?
• How does we design the Truth Table of SR Flip Flops?
• What are further classes of SR Flip Flips?
• Implementation of SR Flip Flops in Proteus.

Flip Flops

Flip Flops are extremely important Circuits of Digital Logic Design. We Introduce the Flip Flops as:

"Flip Flops are type of sequential Logic Circuit that contain two stable states "Zero" and "One" (because of the binary system). It is often used as Storage device and each state of Flip Flop stores one bit." 

They are the building blocks of the Electronics and play an important role in the world of Logic Circuits. Being the Binary circuits, they are essential for the computation in the computer system. The Inputs of the Flip Flops are named as "S" AND "R" that stands for Set and Reset respectively. There are two Outputs of the Flip Flop called Q and Q'. As the name suggest itself, both the outputs are the Inverse of Each Other. the Flips Flop are sequential Logic Circuits that mean they use a Clock called as "CLK"  in the circuit. the Function of clock is to synchronize the circuit. The Phenomenon in which the clock signal is change its value i.e, from 0 to 1 or from 1 to 0, is called the edge of the clock.

DID YOU KNOW?????????????????

Flip Flops are also called as Bipolar Multi-vibrator because they can store the both the Conditions of the Binary system.

When we say that Flip Flops are the Storage Devices, we mean that they does not only calculate the output from the present data, but they can also work with the data stored previously in the Flip Flops.  

Types of Flips Flops

When we talk about the types of Flip Flops, we consider mainly Four types of Flip Flops as follow:

1. SR Flip Flop
2. JK Flip Flop
3. D Flop Flops
4. K Flip Flops

These kinds are same in the composition of circuits, but the working, Construction and the results are different from each other. We'll Describe the structure of each of them along with the simulation for best concepts one after the other.

DID YOU KNOW??????????????

Flip Flops can maintain a binary state as long as there is power in the circuit, therefore can store the Data.

SR Flip Flop

The full name of SR Flip Flop is Set Reset Flip Flop. In this type of Flip Flop the Value of Output Q depends upon the Value of the "S" input. once the input of the SR Flip Flop goes high (When S and R are high) the output goes to infinity or undefined therefore this Circuit is used to  store the information.

Truth Table of SR Flip Flop

When we talk about the Truth Table of SR Latch, we find some unique behavior. The Interesting point about the SR Latch is when Set and Reset are LOW i.e, 0 then the value of the Output does not change. The circuit does not show any alternation. Moreover, when the values of inputs are HIGH, the output is undefined as discussed above. Hence the design of Truth Table of SR Flip Flop is as follow:

S	R	Q	Q’
0	0	No change	No change
0	1	0	1
1	0	1	0
1	1	Undefined	Undefined

  The SR Flip Flops are further classified into two main types:

1. Active High SR Flip Flops.
2. Active Low SR Flip Flops.

we'll learn about their details and the structure of the circuit.

Active High SR Flip Flops

The Active High SR Flip Flops are the one in which the Set input and the output terminal Q collaborate with each other. When the S is 0, the output Q is 1 and vise versa. We know that Q is always opposite to Q' hence we get the output as expected. Let's Look at the circuit of Active High SR Flip Flop and work at it in Proteus ISIS.

Active High SR Flip Flops in Proteus ISIS

• Fire Up your Proteus Software.

Material Required

1. AND Gate
2. NOR Gate
3. NAND Gate
4. Logic Toggle
5. LED-Red
6. Clock
7. Ground Terminal
8. Connecting Wires

• Click at the "P" button and Write AND Gate, NOR Gate, Logic Toggle, LED-Red, Clock one after the other and choose them through Enter button.
• Choose AND Gate from the Pick Library section and arrange two of them at the working area.
• Get two NOR Gates and arrange them just after the AND Gates.
• Get two Logic Toggles and Arrange them just before AND Gate for input.
• Choose two LEDs and fix them just after the NOR Gates.
• Ground each LED through ground Terminal Found in the Terminal modes at the left side of screen.
• Use a Clock in between AND Gates.
• Join all the components through wires just like the image given below:

Now Pop the Play button. Alter the Values of Input and observe all the outputs at each Logic Gate. You will get following Truth Table:

S	R	1	2	Q	Q’
0	0	0	0	No change	No change
0	1	0	1	0	1
1	0	1	0	1	0
1	1	Undefined	Undefined	Undefined	Undefined

DID YOU KNOW???????????

The inputs of Active Low SR Flip Flops are denoted by a a bar , a complement or a "not" word along with their name.

Active Low SR Flip Flop

The Active Low SR Flip Flops have the same output as their twin Circuit Active High SR Flip Flop. The difference is in the construction of the circuit. We use the NAND Gate in the Construction of Active Low SR Flip Flop. all other arrangements and devices are same as the previous one.

Simulation of Active Low SR Flip Flop in Proteus ISIS

• In the above Circuit of Active High SR Flip Flop, pop the left click at gate 1.
• Left click>Delete the Gate 1.
• Repeat the same step with other gates as well.
• Add the NAND gate in all the places.
• Arrange the system again as shown in the figure below:

When we Test the Active Low SR Flip Flop we get the following outputs:

S'	R'	1	2	Q	Q’
0	0	0	0	No change	No change
0	1	1	1	0	1
1	0	1	1	1	0
1	1	Undefined	Undefined	Undefined	Undefined

Hence this is another form of SR Flip Flop. Consequently, we learned about the Flip Flops, we saw what are its types , saw the subclasses of the Flip Flop and designed two types of SR Flip Flops in Proteus ISIS. Stay tuned for the other tutorial in which we'll solve the problem of undefined conditions of Flip Flops.

Half Adder through XOR with AND Gate in Proteus ISIS

Hello Pupils! I welcome you to The Engineering Projects. I hope you are having a good day. In our previous lectures, we simulated almost all the DLD Logic Gates i.e. AND, OR, NOT, NOR, NAND, XOR and XNOR. I hope now you must have a complete understanding of the logic gates and their working.

Now, it's time to have a look at the reason for inventing these logic gates. These DLD logic gates are used to design different numerical modules i.e. adder, subtracter, multiplexer, de-multiplexer, encoder, decoder etc. These arithmetic modules are normally used in electronic products i.e. a simple microcontroller has numerous adders/subtractors for properly calling the registers' addresses.

So, from today onward, we are going to discuss these applications of logic gates one by one. Today, we will focus on the basic one i.e. Half Adder. First, we will understand its working and later will simulate it in Proteus.

Let's have a look at what we'll learn today.

1. What is an Adder?
2. What is Half Adder?
3. Truth Table of Half Adder.
4. Half Adder Simulation in Proteus.
5. Advantages of Half Adder.
6. Disadvantages of Half Adder.

Let's start the Learning.

What is Adder?

• In DLD, an Adder is a simple digital circuit, designed using logic gates and is used to add binary numbers(normally bits).
• Advance Adders can also add other number systems i.e. Binary Coded Decimal, HexaDecimal etc.
• There are two types of Adders, named:
• Half Adder
• Full Adder. (We will cover it in the upcoming lectures)
  

Now, let's have a look at the definition of Half Adder:

What is Half Adder?

• A Half Adder is a simple arithmetic electronic circuit, designed using logic gates to add two binary numbers.
• A Half Adder produces two Outputs of 1-Bit each. These outputs are the Sum and Carry of the added numbers.
• The numbers being added(i.e. inputs of Half Adder) are called augend and added.
• A simple Half Adder is shown in the below figure:
  

• We will understand the working of Half Adder in the next section but for now, we can see in the above figure, the Adder circuit has two inputs and 2 outputs.
• The first output is Sum Bit and the second one is Carry Bit.
• A simple Block Diagram of Half Adder is shown below:

Logical Circuit

In order to design a DLD Half Adder, we will need to use the following two logic gates:

1. XOR Gate
2. AND Gate

If we recall from our previous lectures on logic gates, the XOR Gate is used to provide the Sum of the Inputs, while the AND Gate provides the Carry of the Inputs. So, by combining these two gates, we can easily get both the Sum and the Carry.

Mathematically,

  SUM = A XOR B

CARRY = A AND B

• Here's the Truth Table of XOR Gate:

A	B	Z
0	0	0
0	1	1
1	0	1
1	1	0

• The Truth Table of AND Gate is given below:

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

Let's move towards the Practical implementation of Half Adder in Proteus ISIS.

Simulation of Half Adder in Proteus

To design the circuit of Half Adder, we need the following components:

Components Required:

1. AND Gate.
2. XOR Gate.
3. Logic toggle.
4. LED.
5. Ground Terminal.

Circuit Diagram of Half Adder

• Select the first four components from the Proteus Library.
• Place the XOR Gate and AND gate in the Proteus Workspace.
• Connect the Logic Toggles on the Inputs of the XOR Gate.
• Join the inputs of AND Gate with the Inputs of XOR Gate.
• Connect the LEDs with the output Terminals of both Gates.
• Add the ground terminal with both LEDs.
• The below figure shows the Half Adder Circuit in all possible scenarios:

• Here's the Truth Table of Half Adder:

Input		Output
A	B	Sum	C0
0	0	0	0
0	1	1	0
1	0	0	0
1	1	1	1

Advantages of Half Adder

1. Half Adders are simple in construction & easy to design.
2. We can get a Half Subtractor simply by inverting the circuit.

Disadvantages of Half Adder

1. There is no mechanism to use the carry in the next addition.
2. Can perform very specific functions.

So, that was all for today. I hope you have enjoyed today's lecture. Today, we designed the Half Adder using AND and XOR gates. In the next lecture, we will design the Half Adder using Universal Gates i.e. NAND and NOR gates. Till then, take care. Have fun!!!

Half Adder with Universal Logic Gates

Hello Pupils! I welcome you to The Engineering Projects. I hope you are having a good day. In our previous lecture, we discussed Half-Adder Circuit Designing with XOR and AND logic gates. Today, we are going to design the same circuit using universal logic gates i.e. NOR and NAND gates.

We are going to learn the following topics, in today's lecture:

1. What is Adder?
2. What is Half Adder?
3. How can We make Half Adder Circuit through NAND Gate?
4. How can We make Half Adder through just NOR Gate?

Hence without wasting time, Let's find all the Answers.

What is Adder?

As we discussed in the last lecture, the DLD Adder is a simple electronic circuit, used to add binary numbers in bit form.

There are two types of DLD Adders, named:

1. Half Adder
2. Full Adder

In this article, we'll focus on the Half Adder only.

What is Half Adder?

Let's recall it as well from our previous lecture, a Half Adder is a simple electronic circuit, designed with logic gates and is used to add two binary numbers. It generates two output bits i.e. Sum Bit and Carry Bit.

In our previous lecture, we designed the Half Adder using two types of Logic Gates i.e. AND and XOR but today, we are going to use a single type of logic gate(Universal Gate) to design a Half Adder. As we know there are two universal gates in DLD i.e. NOR and NAND. So, we will design the Half Adder circuit with both of these Universal Gates, shown in the below figure:

Truth Table of Half Adder

• The Truth Table of the Half Adder is shown in the below table:
  

Input		Output
A	B	Sum	C0
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Half Adder with NAND Gate

Let's first recall the NAND Gate:

"A NAND Gate is an inversion of AND Gate and gives LOW output if all of its Inputs are HIGH, otherwise gives HIGH output".

The Truth Table of NAND Gate is shown below:

A	B	(A.B)'
0	0	1
0	1	1
1	0	1
1	1	0

Let's rush towards the Proteus software to run our Half Adder.

Components Required

We will need the following components to design Half Adde circuit in Proteus:

1. NAND Gate
2. Logic Toggle
3. LED
4. Ground Terminal

Proteus Simulation of Half Adder

• Here's the Circuit Diagram of the Half Adder with the NAND gate in Proteus:
  

• For designing the Half Adder circuit, we'll need 5 NAND gates in total, so get them from Proteus Library and place them in the Workspace, as shown in the above figure.
• I have used two Logic States at the Inputs and two LEDs at the Outputs.

In order to understand this Half Adder circuit, let's create a truth table of output at each NAND Gate:

Input		Output
A	B	1	2	3	4(SUM)	5(CARRY)
0	0	1	1	1	0	0
0	1	1	1	0	1	0
1	0	1	0	1	1	0
1	1	0	1	1	0	1

 

Half Adder with NOR Gate

Let's recall the NOR Gate from our previous lecture:

"A NOR Gate is an inversion of the OR Gate and gives HIGH Output only if all of its Inputs are LOW, otherwise it gives LOW".

The Truth Table of NOR Gate is as follows:

A	B	(A+B)’
0	0	0
0	1	0
1	0	0
1	1	1

To implement the Half Adder with NOR Gate, we are going to use the below components:

Components Required:

1. NOR Gate.
2. Logic Toggle.
3. LED.
4. Ground Terminal.
5. Connecting wires.

Proteus Simulation of Half Adder

Here's the circuit diagram of the Half Adder with NOR logic gate:

As you can see in the above figure, we have used 5 NOR gates in total and have placed logic states at the inputs and LEDs at the outputs.

Here's the truth table of Half Adder with NOR Gate:

Input		Output
A	B	1	2	3	4(SUM)	5(CARRY)
0	0	1	1	1	0	0
0	1	0	0	1	1	0
1	0	1	0	0	1	0
1	1	0	0	0	0	1

So, that was all for today. In the next lecture, we will discuss the 2-Bit Full Adder in detail and will simulate it in Proteus. Thanks for reading.