The Engineering Projects

XOR Gate with Truth Table in Proteus

Hey pals, we hope you are doing well. In our previous lecture, we discussed the basic DLD Basic Logic Gates and simulated in Proteus. Today, we are going to discuss another logic gate called Exclusive OR Gate(XOR Gate). We will also design the XOR Gate in Proteus using the basic logic gates(i.e. AND, OR and NOT), discussed in the previous lecture.

In today's tutorial, we are going to focus on:

1. What are Exclusive OR Gates
2. Experimental Proof in Proteus ISIS.
3. How Truth Table of Exclusive OR Gate is designed.
4. How is its Timing Diagram?
5. Circuit of Exclusive OR Gate in Proteus Simulation
6. Applications of Exclusive OR Gates

Exclusive OR Gate(XOR Gate)

• In the Exclusive OR Gate(XOR Gate), the output will be HIGH(1), only if the odd no. of inputs is HIGH(1) and at least one of the inputs is LOW. (it's a bit complex, will understand it in the next section)
• The XOR Gate is denoted by a plus sign with a circle around it between the inputs i.e. $A\oplus B$.
• XOR gate is designed by combining standard logic gates(i.e. AND, OR and NOT), but because of its extensive use in arithmetic operations and error detection, it's considered a standard logic gate.
• The Truth Table of XOR Gate is given below:

A	B
0	0	0
0	1	1
1	0	1
1	1	0

• The XOR Gate symbol along with its representation and truth table is shown in the below figure:

Working Principle of XOR Gate

Its definition has two conditions in it:

1. Odd no. of Inputs should be HIGH
2. At least one of the inputs should be LOW

We have seen in the 2-Input XOR truth table, the output is HIGH in the 2nd and 3rd Rows, because these rows are fulfills both conditions i.e., we have an odd no of HIGH inputs(1 input is HIGH) and at least 1 LOW input(1 Input is LOW). While, in the 1st and 4th rows, both conditions are unfulfilled, thus getting LOW at the output.

Now, let's have a look at the truth table of the 3-input XOR Gate:

Image

Now it will get more clear, as you can see in the 4th row, we have 1 HIGH Input and 2 LOW Inputs, thus both conditions are fulfilled and we are getting HIGH at the OUTPUT. But in the 7th row, 2 Inputs are HIGH and 1 is LOW, although the 2nd condition is fulfilled i.e. we have at least 1 LOW input but the first condition is unfulfilled i.e. we have even no of HIGH Inputs. That's why we are getting LOW at the output. I hope now it gets clear.

Mathematical Representation of XOR

Now let's understand the output of the XOR gate mathematically. XOR gate is used in arithmetic calculations because it adds the inputs and gets the carry.

Here's the mathematical calculation of XOR truth table:

 0+0=0

0+1=1

1+0=1

1+1=0 (Carry)

Here's the Proteus demonstration of the XOR truth table:

Design XOR Gate with Standard Logic Gates

Now, we are going to design an XOR gate using the basic logic gates i.e. AND, OR and NOT. The formula for XOR Gate is as follows:

Y = A.(B)' + (A)'.B

As you can see in the above equation, we can get an XOR output(Y) by applying 3 logic gates i.e. AND, OR and NOT, on the inputs(A and B).

Let's verify this equation by putting values from the XOR truth table:

For 1st Row:

=0.(0)'+(0)'.0

=0.1+1.0

=0+0

=0

For 2nd Row:

Now, A=0, B=1:

=0.(1)'+(0)'.1

=0.0+1.1

=0+1

=1

For 3rd Row:

Consider A=1, B=0:

=1.(0)'+(1)'.0

=0.1+0.0

=1+0

=1

For 4th Row:

At last, check the expression when A=1, B=1:

=1.(1)'+(1)'.1

=1.0+0.1

=0+0

=0

So, now let's design this equation for the XOR Gate in the Proteus software. Let's get started:

Proteus Simulation of XOR Gate

As we have seen in the previous section, we need to implement this equation in the Proteus software:

Y = A.(B)' + (A)'.B

So, open your Proteus software and get these components from the Proteus library:

Material Required:

1. AND Gate
2. OR Gate
3. NOT Gate
4. Logic Toggle
5. LED

Circuit Diagram of XOR Gate:

Here's the circuit diagram of the XOR Gate in Proteus using the standard logic gates i.e. AND, OR and NOT:

• As you can see in the above figure, the upper AND gate is implementing the first part of the equation i.e. A.(B)' and the second AND gate is implementing the second part i.e. (A)'.B
• NOT Gate in inversing the inputs, placed at the inputs of AND Gates.
• Finally, we placed an OR gate to add the outputs from both AND gates so that we could complete the equation i.e. A.(B)' + (A)'.B 
• Finally, we placed an LED at the output.

Applications of XOR Gate

XOR Gate is used in many circuits as:

1. We use XOR Gate in Half Adder.
2. It is used in the circuit of Controlled inverters.
3. XOR is also used in comparators.
4. Subtractor is the application of XOR Gate.
5. The parity checker is made through XOR Gate.
6. XOR is used in the Arithmetic Logic Circuits.
7. Circuit of Binary to Grey and vice versa.

Today, we discussed the Exclusive OR Gate in detail. We have also designed the simulation of XOR Gate in PRoteus software with the help of basic logic gates i.e. AND, OR and NOT gates. That's all for today. Take care!!!

XNOR Gate with Truth Table in Proteus ISIS

Hello Mentees!, I hope you have a productive day. Welcome to The Engineering Projects. In the previous lecture, we discussed the XOR Logic Gate and designed its circuit using basic logic gates i.e. AND, OR and NOT. Today, I am going to explain another Logic Gate named XNOR Gate in detail.

We are going to discuss these concepts in today's lecture:

1. What are Exclusive NOR Gates
2. Experimental Proof in Proteus ISIS.
3. How Truth Table of Exclusive NOR Gate is designed.
4. How is its Timing Diagram?
5. Circuit of Exclusive NOR Gate in Proteus Simulation
6. Applications of Exclusive NOR Gates

XNOR Gate

• The exclusive NOR Gate(also called XNOR Gate) simply inverts the output of the XOR Gate(we discussed in the last lecture).
• So, if we simply place a NOT Gate in front of the XOR Gate, we will get the XNOR Gate.
• The XNOR Gate is denoted by a plus sign with a circle around it between the inputs and a collective Complement or a Bar on the Expression.
• The symbolic representation of XNOR along with symbol and expression is shown in the below figure:

• The Truth Table of XNOR Gate is given next:

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	1

Mathematical Expression of XNOR Gate

The XNOR Gate with 2-inputs(A and B) and 1 Output(Z) is represented by the following mathematical expression:

Z = (A)'.(B)' + A.B

So, we will need AND, OR and NOT logical gates to implement XNOR Gate. Let's first verify this equation by applying the truth table.

For 1st Row:

=(0)'.(0)'+0.0

=1.1+0.0

=1+0

=1

For 2nd Row:

Now, A=0, B=1

=(0)'.(1)'+0.1

=1.0+0.1

=0+0

=0

For 3rd Row:

Consider A=1, B=0:

=(1)'.(0)'+1.0

=0.1+1.0

=0+0

=0

For 4th Row:

Lastly, A=1, B=1:

=(1)'.(1)'+1.1

=0.0+1.1

=0+1

=1

Hence in accordance with the above discussion, let's design the circuit of the XNOR Gate in the Proteus software:

Proteus Simulation OF XNOR Gate

Now let's design the Proteus Simulation of the XNOR gate. We simply need to implement the mathematical expression of XNOR Gate, discussed in the last section.

Material Required:

1. AND Gate
2. OR Gate
3. NOT Gate
4. Logic Toggle
5. LED

Circuit Diagram of XNOR Gate:

First of all, we will design the below circuit in Proteus:

Image

As you can see in the above figure, the first AND Gate is getting the inverted inputs and the second AND Gate is provided with simple inputs. Finally, the output of both AND gates is passed through the OR Gate and we got our XNOR output. I have placed an LED at the output to visualize it.

Applications of XNOR Gate

XOR Gate is used in many circuits as:

1. We use XOR Gate in digital circuits.
2. It is used in error-detecting Circuits.
3. XOR is also used in Arithmetic Circuits.
4. Encryption Circuits is the application of XNOR Gate.
5. The combinational circuit is made through XNOR Gate.
6. XNOR is used in sequential Circuits.
7. Circuit of Binary to Grey and vice versa.

Today we saw discussed the Exclusive NOR Gate(XNOR Gate) in detail. We have also designed its simulation using AND, OR and NOT logic gates. Till the next tutorial, take care!!!

4-Bit Full Adder using Logic Gates in Proteus

Hi Learners! I hope you are having a productive Day. Welcome from the Team of The Engineering Projects. The digital logic circuit that we are learning today is 4-Bit Full Adder. In our previous tutorial, we designed 2-Bit Full Adder using Logic Gates in Proteus software. Today, we are going to design & simulate 4-Bit Full Adder using Logic Gates in Proteus.

We will discuss the following topics in today's lecture:

1. What is Adder?
2. What is Full Adder?
   
3. Working Principle of 4-bit Full Adder.
   
4. Simulation of four-bit full Adder in Proteus ISIS.

What is Adder?

Let's recall the Adder Definition from our previous lectures:

• Adders are Digital Logical Circuits, specially designed to add two or more binary numbers or bits.

In the world of electronics, adders are used to add bits. The computer system depends upon the flow of bits and the computation of bits. Adders take the input in the form of bits and perform the addition, according to the type of Adder used. Basically, we divide the adders into two types:

1. Half Adder.
2. Full Adder.

We have discussed both Half Adder & Full Adder in detail in our previous lectures. Yet we have to recall the full adder's introduction:

What is Full Adder?

"Full Adders are the Digital Logic Circuits used to add three input bits and generate two outputs i.e. the Sum and the resultant Carry."

We further classify the Full Adder into two main types:

1. 2-bit Full Adder.
2. 4-bit Full Adder.

4-bit Full Adder

As the name implies, a four-bit full adder is used to add four sets of input bits. The definition of a 4-bit Full adder is as follows:

• "A 4-bit Full Adder is designed to generate a 4-bit Sum and is designed by combining four 2-bit Full Adders and as a result shows the Four bits output along with the Carry Bit."

The Circuit of the Four-bit Full Adder consists of the XOR Gate, AND Gate and OR Gate. Let's have a quick recap of these Gates.

XOR Gate

A XOR Gate, is a two input Logical Circuit that give the output HIGH only when the inputs have the values alternating of each other. Or else, it is LOW.

AND Gate

AND Gate is the a logical Circuit that gives the Output HIGH only when its both inputs are HIGH, otherwise the output is LOW.

OR Gate

The OR Gate is a logical Circuit with the working such that when on of the Input is HIGH, the value of the Output is also HIGH.

Working Principle of 4-bit Full Adder

The Four Bit Full Adder works in an interesting manner. The XOR Gates are responsible for the addition of input bits. In order to get the full addition circuit we attach two AND gates with the circuit in such a way that the result of addition connects the OR Gate and we get the carry.

In the designing of circuit, we simply make a small circuit of AND Gate and XOR Gate. Then we design a Circuit of two bits Full Adder. The cynosure of the circuit is, we'll copy the block and arrange four blocks in a way that the output carry of the block becomes the input carry of the next. This cycle will continue and at the  fourth block we get the resultant carry of whole calculation. we can input only one carry of our will at the Block A.

Practical performance of 4-Bit Full Adder

If you wish to stimulate the Four bits full adder in Proteus then follow the simple steps given below. We'll make our circuit according to the Functional Diagram given before.

• Begin Your Proteus Software.
• Get the required material.

Required Devices

1. XOR Gate
2. AND Gate
3. OR Gate
4. Logic Toggle
5. LED
6. Ground Terminal

• Push the "P" button presented at left area of the screen.
• Select first four elements from the Library by mere writing there names one after the other.
• Get  a XOR Gate and one AND Gate.
• Connect the Logic Toggles with each input of XOR Gate.
• Connect an LED with the end of the XOR Gate.
• Go to Terminal Mode and get the ground terminal to attach the Ground Terminal with LED.
• Drag and drop two XOR Gates, two AND Gates and one OR Gate and arrange them at the working area one after the other according to the image given below:
• Attach Logic Toggle with each input of switch 1.
• Get the LED and join it with the output of switch 3.
• Click the left button of mouse> go to Terminals> Ground Terminal.
• Place the ground Terminal just below the LED.
• Join all the components according to the images given below;

 

• Select the whole block left click>drag and drop the required area. It will create a doted square around the circuit.
• Right Click> copy block.
• Right click the mouse and paste the block with the same procedure.

• Repeat the Pasting Process one time more and paste the circuit copy just one below the other.
• Connect the each output carry switch with the input of the next.
• Grab the Logic Toggle from the Pick Library and join it with the input carry wire of the first block.

• Change the input values by the mean of Logic Toggles and check the working.

Working Example of 4-bit Full Adder in Proteus

You can test the circuit with an example. Question: We have two numbers 1100 and 1010. Find the resultant through four bits Full Adder. Answer: Let A=1100 B=1010

Logic about For bit Full Adder

The 1st Logic Toggle of each XOR 1 switch is called A bit. The 2nd Logic Toggle of each XOR 1 represents the B bit. Turning of LED means the HIGH (1) and vise versa. We start to input from down to up and the output as well. Hence start the observation from block D to A.  For the Question, the circuit should be set as: Hence we got the answer that is:

A	1	1	0	0
B	1	0	1	0
Result	(1 carry)0	1	1	0

Consequently, we made a Four bit Full Adder. Stay tuned for other Logical Circuits.

2-Bit Full Adder using Logic Gates in Proteus

Hello Learners! I hope you are doing great. Welcome to The Engineering Projects. In our previous lecture, we discussed How to design Half Adder with Universal Gates. In today's tutorial, we are going to design Full Adder with Logical Gates.

In today's tutorial, we will learn the complete information about:

1. What is Adder?
2. What is Full Adder?
3. How is the Truth Table of Full Adder?
4. How can we design Full Adder in Proteus ISIS?
5. What are the uses of Full Adder?

What is Adder?

Recalling from our previous lectures:

• The Adders are simple Logical Circuits that take the bits in as the input, sum the bits together and generate the sum and the carry at the output.
• Adders are present in computer architecture, mainly to control the addressing of the Arithmetic Logic Unit(ALU).

We classify the Adders into two types:

1. Half Adder.
2. Full Adder.

We have discussed half Adder in detail in our previous two lectures. Today we'll stress the Full Adder:

What is Full Adder?

There are two types of Full Adders:

• 2-bit Full Adder.
• 4-Bit Full Adder. (We will discuss in the next lecture)
  

We define the Full Adder as:

•  A Full Adders is a simple Logical Circuit, that takes 3 inputs(1-bit each) and generates two outputs i.e. the Sum(1-bit) and the Carry(1-Bit).
• A Full Adder takes 2 inputs A and B, while the third input is actually the Carry Input.

• We have seen in the Half Adder that we took 2 inputs and calculated the Sum and the Carry but we have no way of adding that Carry back into the Sum.
• This problem is solved by the Full Adder, which takes the Carry and adds it in the Sum to get a final Sum.
• That's why, we can use multiple Full Adders in series to add any amount of Bits.
• For example, we can serially attach 8 Full Adders to add 8 Bits of data(1-byte).

The Full Adder plays an important role in computer hardware calculations i.e. ALU control, register addressing etc. Here's a simple 2-Bit Full Adder Circuit using Logic Gates:

Truth Table of 2-bit Full Adder

As discussed above, there are three inputs and two outputs present in Full Adder. Therefore, the Truth Table of Full Adder will have 5 columns in total:

The input combinations of the Truth Tables are followed through the formula:

Numbers of Combinations= 2^n

where n is the number of inputs. In our case,

n=3

hence,

Numbers of Combinations=8

We start the truth table from zero bit. The right most input has the alternative inputs after each combination. The middle contains the alternative bits after two combinations. By the same token the left most changes the input bit after four combinations.

The Truth Table of Full Adder looks like this:

A	B	Cin	Sum	C0
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1
Carry+A+B			Sum	Carry out

Simulation of Full Adder in Proteus ISIS

To design a Full Adder in Proteus, get these components from the library:

Components Required

1. XOR Gate
2. AND Gate
3. OR Gate
4. Logic Toggle
5. LED
6. Ground Terminal

• Get the first five components from the Pick Library through the "P" button.
• As shown in the below figure, I have placed the 5 Logic Gates in our Proteus workspace.
• We have 2 XOR Gates at the top, after that we have 2 AND Gates and finally an OR Gate at the end.
• The circuit should look like this:

• Now, connect two Logic Toggles with the inputs of Logic Gate 1.
• Connect one Logic Toggle with the 2nd input of Logic Gate 3.
• Attach the LED with the Gate 3 output and ground the LED with Ground Terminal present in "Terminal Mode" on the leftmost bar of the screen.
• Repeat the above step for Logic Gate 5.
• Connect all the Logic Gates according to the diagram given next:

• Change the Input bits and record your own truth table.
• To understand the working better, we'll design a Truth Table that describes the output of each Logic Gate.

Input			Output
A	B	Cin	Gate1	Gate2	Gate4	Gate3(Sum)	Gate5 C0
0	0	0	0	0	0	0	0
0	0	1	1	0	0	1	0
0	1	0	1	0	0	1	0
0	1	1	0	1	0	0	1
1	0	0	0	0	0	1	0
1	0	1	1	0	1	0	1
1	1	0	1	0	1	0	1
1	1	1	0	1	0	1	1
Carry+A+B						Sum	Carry out

Truss, we got a Full Adder circuit through which we can make the calculations.

Uses of Full Adder

1. Full adders are paramount for the on-chip Libraries.
2. They are used in computers for table indices.
3. They are used by the processor to add the addresses.
4. Full adders are used in Arithmetic Logic Unit.
5. Full Adders are used in the Computer for the series calculations. For this purpose, they may be connected in the way given next in the image. Observe it from bottom to top.[TEPImg6]
6. It can be designed so, that we can input eight bits together that collectively work as a byte.

So, that was all for today. We discussed What are Adders? What are Full Adders? Truth Table of Full Adder and how can we design Full adder in the Proteus software. I hope this article was useful. In our next lecture, we will discuss 4-Bit Full Adders in detail. Thanks for reading.

What are DLD Logic Gates? Symbol | Truth Table | Simulation

Hello Mentees! I hope you all are doing well. In today's article, we'll learn about the very basic pillar of Digital Logic Circuits i.e. Logic Gates. As we know, the digital world depends on Boolean digits either 0 or 1. So, there's always a need to perform different operations on these boolean numbers i.e. addition, subtraction, multiplication, shifting etc. In order to perform these operations on the binary signals, we use Digital Logic Gates in DLD circuits.

So, let's have a look at What is a Logic Gate:

What is a Logic Gate?

• Logic Gates are designed to perform a specified operation(i.e. addition, bit shift etc.) on the input signals and generate the output signal.
• For example, a simple NOT gate takes a single binary input and returns its inverse in the output, i.e.
• If Input is 0, the Output will be 1.
• If Input is 1, the Output will be 0.
  
• We can design Logic gates using basic electronic components i.e. resistor, diode, transistor, etc. However, in order to design gates for commercial use, two main manufacturing technologies are used, i.e:
• TTL(Transistor-Transistor Logic): TTL Logic gates use NPN & PNP Bipolar Junction Transistors in their circuitry i.e. 7400 series.
  
• CMOS(Complementary Metal Oxide Silicon): CMOS Logic Gates use MOSFET or JFET transistors(i.e. 4000 series)yea ri and are quite popular because of their ultra-quick response.
  

Symbolic Representation

• Each Logic gate is assigned a symbol for its representation, which simplifies the designing of their circuit diagrams.
• The symbolic representation of 4 basic logic gates is as follows:

Truth Table

• Every logic gate has a truth table(also called a logical table), used to provide the output states for all the possible combinations/conditions of its inputs.
• It's a convention to write the outputs in the right-side columns and the inputs in the left-side columns.
• The truth table of NOT Gate(used to inverse input), is shown in the below figure:

Input	Output
0	1
1	0

• As you can see in the above figure, the table has 2 rows in total giving us all the possible input conditions.
• The number of rows in a truth table depends on the number of inputs used. The formula is, if we have "n" number of inputs in a logic gate, its truth table will have 2ⁿ rows in total. So, if we have 2 inputs, the rows of its truth table will be 2² = 4.

Truth tables are useful in Boolean and mathematical operations as the relationship between the Input and Output can be understood at a glance.

Now let's have a look at the Circuit Designing of Logic Gates:

Logic Gates Circuit Designing

As we discussed earlier, different Manufacturing Techniques are used to design logic gates. These techniques decide the characteristics of the logic gates i.e. response time, noise immunity, voltage level for logic shifting etc. We can use simple electronic components i.e. diode, transistor, resistor etc. to design logic gates. The normal practices for designing logic gates with simple electronic components are:

• RTL (Resistor-Transistor Logic)
• DTL ( Diode-Transistor Logic)
• ECL (Emitter-Coupled Logic)
• DRL (Diode-Resistor Logic)

Such logic gates are quite simple in designing and normally have quite low response time and may also provide false output because of noise. So, in order to overcome these issues, these two manufacturing techniques are used:

• TTL(Transistor-Transistor logic)
• CMOS(Complimentary Metal oxide Semiconductors)

Simple NPN and PNP transistors are used in TTL logic gates and thus have better response time as compared to basic logic gates. In the CMOS technique, MOSFET and FET are used to control the logic and thus provide the best response time and are quite immune to noise. So, among all these manufacturing techniques, CMOS is considered the most popular technique for logic gate designing.

Logic Gates Designing with Basic Components

Here is an example of an AND Gate design with a Diode-Resistor Logic(DRL) and a NAND gate designed with Diode-Transistor Logic (DTL):

As you can see in the above figure, these circuits are quite easy to design, as simply using diodes, resistors, and transistors. But these circuits are not used in commercial ICs because of their high power loss(pull-up resistor) and gate delay(propagation delay). That's why, CMOS and TTL are considered the better option to design digital logic gates.

TTL Logic Gates

In TTL Logic Gates, NPN and PNP transistors are used for designing logic gates. The ideal TTL logic gate is the one that gives the LOW(0) Logic at 0V and HIGH(1) Logic at 5V. In a real TTL Logic Gate, the logic will be considered LOW(0), if the voltage level lies between 0-0.8V and the logic will be considered HIGH(1), if the voltage level is in the range of 2-5V. The voltage level between 0.8-2V is considered a "no man's land" and normally external pull-up or pull-down resistors are used to avoid this region. Examples of TTL Logic Gates ICs are 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx etc. The switching voltage varies from group to group according to their internal structure and material used. 

CMOS Logic Gates

In CMOS Logic Gates, FET(Field Effect Transistor) and MOSFET are used to design the logic gates. CMOS logic gates provide a LOW(0) logic, if its voltage is in the range of 0-1.5V and it will give HIGH(1) logic, if it's in the range of 3-18V. The below table shows the voltage levels of both TTL and CMOS logic Gates:

Logic Gates	LOW(0)	HIGH(1)
TTL	0-0.8V	2-5V
CMOS	0-1.5V	3-18V

Now, let's have a look at the Types of Logic Gates:

Types of Logic Gates

• There are numerous types of Logic gates available based on the quantity of input/output channels and the type of logic to be applied.
• Based on the specified logic, gates are divided into 3 basic types, i.e.
1. AND Gate.
2. OR Gate.
3. NOT Gate.
• These 3 basic gates are the building blocks of all advanced logic gates. So, we can design any advance logic gate with these 3 basic logic gates.
• The most commonly used Advance Logic Gates are:
1. NAND Gate.
2. NOR Gate.
3. XOR Gate.
4. XNOR Gate.
   

• The above-mentioned 7 logic gates are the most commonly used ones. Following logic gates are not that common but are in practice:
• MIN(Minimum) Logic Gate.
• MAX(Maximum) Logic Gate.
• INH(Inhibit) Logic Gate.
• MAJ(Majority) Logic Gate.
• IMP(IMPLY) Logic Gate.

It's quite difficult to cover all these gates in a single lecture. So, we will only discuss the basic 7 gates i.e. AND, OR, NOT, NAND, NOR, XOR and XNOR. Today, we will have a brief overview of these 7 logic gates but in the upcoming lectures, we will cover each one of these individually in full detail. Here are the symbols of few logic gates:

So, let's get started:

AND Logic Gate

• AND Gate is a basic logic gate and gives  HIGH output, when all of its Inputs are HIGH and generates LOW output, if any of its Inputs got LOW.
• The AND Gate performs the Logical conjunction. We denote it with the DOT between the inputs i.e. A.B = Y where A & B are the inputs and Z is the output.
• The Inputs in AND Gate is always more than one i.e. Inputs >= 2 and it will always generate a single output.
• The logical symbol of the AND gate is shown in the below figure:

Truth Table:

• Here's the truth table of AND gate in tabular form:

A	B	A.B
0	0	0
0	1	0
1	0	0
1	1	1

As you can see in the truth table of AND Gate, the Output is 1 only when both of its inputs are 1, otherwise, it's 0.

Proteus Simulation of AND Gate

Proteus has an AND Gate component in its components library. We are going to use it to verify the truth table of AND Gate. We will use the following components for designing this AND Gate Simulation:

1. AND Gate
2. LED
3. Logic Toggle
4. Ground Terminal

Here's the Proteus simulation of all possible states of the AND Gate with 2-inputs:

• I have placed a Logic State at the inputs of the AND gate and an LED at the output.
• The LED glows only when both of its Inputs are 1(HIGH).

OR Gate

• OR gate performs the Disjunction Logic on the inputs i.e. The output will be 1(HIGH), if any of its Inputs is 1(HIGH) and the output will be 0(LOW), if all of its Inputs are 0(LOW).
• OR Gate is denoted by a plus sign "+" between the inputs i.e. A+B = Y, where A & B are the inputs and Y is the output.
  
• Identical to AND Gate, OR Gate also has a minimum of two inputs and only one output.
• The OR Gate Symbol is shown in the below figure:

Truth Table:

• Here's the truth table for the OR Gate:

A	B	A+B
0	0	0
0	1	1
1	0	1
1	1	1

In the case of OR Gate, the output is LOW, only when all of its inputs are LOW, otherwise its HIGH.

Proteus Simulation of OR Gate

• The simulation is quite the same as that of the AND gate, we simply replace the AND Gate with OR Gate, present in the Proteus components library.
  
• The below figure shows that the output LED is OFF, only when both inputs of OR gate are LOW.
  

NOT Gate

• In Logic Circuits, the NOT Gate performs the inversion.
• This is a unary logic Gate that implies it has only one input and a single output.
• The output of NOT Gate is denoted by a Bar or Complement on the input symbol i.e. If the input is A, the output will be A'.
• Here's the symbolic representation of NOT Gate:

Truth Table:

• Here's the truth table of NOT gate, quite simple isn't it?
  

A	B
0	1
1	0

 

Proteus Simulation of NOT Gate

• Grab the NOT Gate from the Proteus components library.
• Attach LED and logic toggle at output and input respectively.
• Here are the results:

So, today we discussed the basic logic gates i.e. AND, OR and NOT Gate and simulated them in Proteus. In upcoming lectures, we'll use these gates to design advance gates and circuits. Take care!!!

JFET Applications | Constant Current Source | Chopper

Hi Pupils, Welcome to another Experiment of Proteus at The Engineering Projects. Previously, we saw what are the Junction Field Effect Transistors. Today we'll learn about some of the applications of Junction Field Effect Transistors.

Just before the Experiment, it is useful to revise that: Transistors are three terminal, unipolar Devices. The terminals of Junction Field Effect Transistor are named as :

• Drain
• Source
• Gate

The Gate Terminal is common to both Source and Drain. Prior to start, let's clear some Concepts about Junction Field Effect Transistor.

Resistor

Resistor is an electrical device. we define the resistors as:

"A Resister is a two terminal Passive electrical device that shows the electrical resistance and is useful in almost every Circuit.

Resistors can be used to reduce or control the flow of current , terminate transition lines and such other functions.

Pinch off voltage

The basic Definition of Pinch off voltage is:

"The voltage applied between the Drain and the source at which the current maximum current flows through the circuit provided the Gate voltage is zero is called the Pinch off voltage."

when the value of voltages is less than the pinch off region, the voltage enters to another region called ohmic region of JFET and the transistor acts as a resistor in this region.

Controlling Voltage

The Controlling Voltage of Junction field effect transistor is defined as: "The controlling Voltage is the voltage of transistors from gate to source.  To set its value, the Voltage from gate to source is made negative and it is referred as Vgs." FET's are widely used in the worlds of electronics because of their size and the performance. We'll apply JFET's in the making of two of circuits:

1. Constant Current Source.
2. Chopper.

During the Implementation of the Circuits, we'll use N-type JFET because of the better flow of electron of this kind of JFET. In N-type JFET the majority charge carriers are electrons. I am going to explain it one after the other.

Constant Current Source

A Field Effect Transistor can be use as a constant current Source. That spell out that if JFET's are designed so, they can provide a constant current across the load resistor, no matter how much current is provided at its input. The ability is due to the near horizontal line in the drain characteristics of the JFET. Recall that resistor is a two terminal Device that reduces the current flow, divide voltage or adjust signal lines. But, carefully Controlled JFET can be used to overcome the resistance through the resistor that come in between the JFET and the Voltage source. In the circuit, when the Vgs is greater than the pinch off voltage. mathematically,

V-IR>|V|

Implementation in Proteus ISIS

To make the circuit for Constant current Source, we need the Components as:

Component Required:

1. Junction Field Effect Transistor
2. Resistor
3. Ground Terminal
4. Direct Current Power Supply
5. Connecting Wires

Procedure

• Fire up your Proteus Software.
• Choose the JFET and Resistor from the Pick library through the "P" button.
• Take the Ground Terminal from Terminals library from the left most tab.
• Take DC power source from the "Generator mode".
• To measure the Current we'll add a DC ammeter from the "Virtual Instrument Mode".

This is the step where the Circuit should be arranged so, to get the required output.

• Connect the Source with the Drain thorough a wire.
• Join the Ground Terminal with the wire that connects Source and Gate.
• Connect the Components on the Working area according to the diagram:

• Double Click the Battery and give it a value of 9 volts.
• Double click the voltmeter and change the display Range to milliamps.
• By the same token, Double tap the resistor and give it the value of 1k ohm.

NOTE: you can also use a variable resistor.

•  Record the values of the ammeter.
• At first observations, Change the value of resistor to 1kohm.
• Pop the play button.

The ammeter shows the value of the 0.40 miliamps.

• Take seven reading by changing the value of resistor and make a table.

  Resistance	Current
  1k ohm	0.40 *10-3
  2k ohm	0.40 *10-3
  3k ohm	0.40 *10-3
  4k ohm	0.40 *10-3
  5k ohm	0.40 *10-3
  6k ohm	0.40 *10-3
  7k ohm	0.40 *10-3

   

The same experiment can be done by varying the value of battery and recording the values.

Chopper

A Chopper is the application of Transistor that show us the output as the square wave. We define the Chopper as: "Chopper is an electronic circuit used to take the amplified Direct current by using some type of transistor or other device." One can use any kind of transistor  e.g Bipolar Junction Transistor tor make the Chopper circuit. But, Junction Field Effect Transistors are better for this purpose due to the field control of the JFETs. In Choppers, the FET act as a variable resistance.   Lets rush towards Proteus to apply the circuit.

Implementation of Choppers in Proteus ISIS

• Fire up your Proteus ISIS.

Material Required

1. Junction Field Effect Transistor
2. Resistor
3. Alternating current source
4. Ground
5. Oscilloscope

• Pick the Vsine , Resistor and JFET from the Pick library by the mean of "P" button.
• Take the Oscilloscope form "Virtual Instrument Mode" and fix it just above the Circuit.
• Connect Channel A just after the AC source and channel B with the Source.
• Put the Ground terminal below the circuit by choosing it from "Terminal".
• Change the value of resistance connected to AC as 100ohm.
• Change the value of resistance connected to Source as 200ohm.
• Give the frequency to 1000Hz and Amplitude of 12V to Vsine.
• Join the circuit according to the image given below:

Seems like our circuit is complete now.

• Press the Play button to simulate the graph.
• Set the Value of Channel A to 1V.
• Set the channel B to 20V.

The Output of the circuit is:   This Conversion is important in some Circuits. The output of the Chopper is in the form of square waves. Thus, today we learnt about the JFET along with the applications of JFET as Constant current and Chopper in detail and saw their Implementation in the Proteus.

What are Digital Latches? | SR-Latches | D-Latches

Hi mentees, we are here with a new tutorial. I hope you all are fine. So far, we have been designing combinational circuits i.e. Adder, Subtractor, Multiplexer etc. using logic gates. But from today onward, we will design sequential circuits using logic gates i.e. Latches, Flip Flops etc. Let's quickly recall what's the difference between combinational & Sequential Circuits:

Combinational Circuits:

• Combinational circuits only use the current state of the input values to generate the output.
• Examples of DLD Combinational Circuits are: Adders, Subtractors, Multiplexers etc.
  

Sequential Circuits

• Sequential Circuits use both the current & previous states of the inputs to generate the output.
• Examples of DLD Sequential Circuits are: Latches, Flip Flops, Timers, Counters etc.

Digital Memory Elements

Normally two types of memory elements are used in digital circuits to store binary data, named:

• Latches
• Flip Flops(We will cover in the next lecture)
  

As today's lecture is on Latches, so let's explore it:

What are Latches?

• Latches are used in digital circuits as a memory element and are used to store/save the input states.
  

The two inputs of Latches are called "S" and "R" where S stands for SET and R stands for RESET. Due to inputs , latches can have four unique combinations of the input. The output is denoted as "Q" and is totally dependent on the input Combination.

Nevertheless, another Output is also used in the circuit sometimes. this output is denoted as Q' and is read as Q bar, Complement of Q or bar Q  NOT Q because it is also written as:

One can have an idea that this output is the invert result of "Q" output and depends on the Q and successively to the inputs S and R.

Two types of circuits are possible in latches:

1. Active high circuits.
2. Active low circuits.

Both of them are same in the Components but are different due to the arrangement of the Components. Active high circuits: In this kind of the Circuit the inputs are grounded and therefore are LOW. Latch are triggered momentary high signal. Active Low Circuits: In this kind the inputs are LOW and the latches are triggered at high signals.

TYPES OF LATCHES

Latches are classified into two main types:

1. SR Latches
2. D Latches.

whereas, 1st two types are further subdivided into two categories:

1. Simple
2. Gated

All of theses types along with the implementations are shown in figure on right side.

Prior to start  DO YOU KNOW???????

• Logic Probes are used to give input to the circuit. They can only give two types of inputs:

1. High ( Denoted by 1)
2. Low ( Denoted by 0)

• By the same token, Logic toggle show the output. There are two types of output:

1. High ( Denoted by 1)
2. Low ( Denoted by 0)

• NAND gate shows the output LOW ( or 0) only when both the inputs are HIGH.
• NOT gate show is an inverter gate.
• NOR gate shows the output HIGH ( or 1) only when both the inputs are HIGH.

Implementation of Latches in Proteus ISIS

For best understanding, we'll design each of the type and create the truth table. Devices Required:

1. AND Gate
2. NOT Gate
3. Three input AND Gate
4. Logic Toggle
5. Logic Probe
6. Clock

Procedure: All the Circuits follow almost same procedure. Even so, they are different in the Construction and the characteristics.

1. SR Latches in Proteus ISIS

• Choose Two NOR Gates and fix them on the working area.
• Examine the Circuit diagram and arrange the other required Components according to the Circuit diagram.
• Truss all the Components by wires with the help of circuit diagram.
• Pop the Play button and fill the truth table.

NOTE: You can also make this Circuit with NAND Gate. Examination: The SR latch ( SET/RESET) mainly change according to the change in the S line. that means, whenever the S is HIGH the Q ( output) is shown as HIGH and vise versa.  but when both the inputs (SET & RESET)  are HIGH then we seen that both the outputs are LOW. Q ( output ) is alway the inverse of Q'. Once we check all the Conditions we can assemble our own truth table. I have made a truth table that shows us the following result:

S	R	Q	Q’
0	0	1	0
0	1	0	1
1	0	0	1
1	1	0	1

 

2. Gated SR Latch in Proteus ISIS

 

The SR latch are not Complete, hence the performance can be enhanced by the a process called "Gating" , and the resultant circuit is called Gated SR Circuit.

• We add two Positive NOR gates at the input "S" and "R" that have inverted input using NOT Gates. In this way we can examine the Condition more clearly when both the inputs in SR gate were HIGH.
• The circuit works well when we add a clock in the two inputs of the NOR gates.

The Circuit of Gated SR is shown next: When we test the Circuit's all conditions , the output have some difference. The output here shows us the difference.  During the LOW conditions of the Circuit the output shows us the error or Latch.

CLK	S	R	Q	Q’
0	X	X	LATCH	LATCH
1	0	0	LATCH	LATCH
1	0	1	0	1
1	1	0	1	0
1	1	1	1	0

3. D Latches in Proteus ISIS

D latch is a modification of the Gated SK Latch.

• we add the NOT Gate in advance of the RESET (R) Input and we get the circuit that looks like this:

  Accordingly to the Picture, the D  and clock are now the inputs of the Circuit and we can notice the output at Q and Q'.

CLK	D	Q	Q’
0	0	NO CHANGE	NO CHANGE
0	1	NO CHANGE	NO CHANGE
1	0	0	1
1	1	1	0

4. Gated D Latch in Proteus ISIS

This is another type of D Latch.

• Connect the clock with the D input so that  we alter the D input. But with this change, we see the changes in the output as well.

Let's have a look on the Circuit of Gated D Latch:   when we change the D and test all the Condition, the resultant truth table is:

CLK	D	Q	Q’
0	0	0	1
0	1	1	0
1	0	1	0
1	1	0	1

Hence today we learnt about the latches, some basic concepts and its types along with  practical implementation.

Introduction and Installation of Emu8086 in windows

Hey Pals, Welcome to the new lesson. I hope you are having a productive day. Today, we'll talk about installation of Emu8086 application in windows. but  before this, It is important to have the brief introduction of the application. Lets find out what is Emu8086.

"Emu8086 is a powerful, offline and  free software for emulation, disassembling and debugging of 8086 programs i.e, 16 bits/DOS." It is an Integrated Development Environment (IDE) that write a source, assemble it and link into .COM or .EXE file then trace it in machine code and source file. When we launch the Emu8086 Asm or Ist will start the assembler source editor. one the other hand, .exe and obj files starts the disassembler and debugger units.

Let's move towards its installation:

Prerequisite:

You must have

1. A PC
2. An active internet Connection
3. Administrative rights for Windows XP/Vista/7 users.
4. 10 Mb of hard disk space
5. 1024x768 or greater screen resolution.

Installation Process:

You can get Emu8086 through the link given below: Introduction and Installation of Emu8086 in windows

• Click it and you will get a Website.
• Click "Download for PC" button. This opens a new tab and the downloading starts.

Observe that the zip file of 3Mb in your folders .

• Click on the small arrow, open the folder. A folder will be pop up.
• Double click at "Setup". It will ask for the permission. Allow it by clicking "yes".

The Window will appear that will start the setup process.

• Click "Next" to continue the process.

A new will be appear like this:

• Close All the Application running applications and click "Next".
• Now, You have to give the path for the folder .By default the path is given for the C directory but you can change it by clicking Browse.

• Read all the tabs appeared after it and then Click "Next".

In the last window, it will ask does we want to launch the Emu8086 or Does we wish to read the instruction.

• Choose the action you want to be launched or mere remove the tick mark and the setup is finished.

The Emu8086 icon will appear on your desktop. You can use it whenever you want. Hence, today we learnt about Emu8086. We saw the brief introduction along will the installation process in detail.

Shunt Clippers and Dual Clippers in Proteus ISIS

Bonjour trainees!!! Welcome to the Engineering projects, We hope you are doing great. In our previous lecture, we discussed the first type of clippers in detail i.e. Series Clippers. Today, we are going to discuss the next two types of Clippers i.e. Shunt Clippers and Dual Clippers. Here are the types of Clippers from the last lecture:

So, today, we are going to cover the below concepts:

1. what is a Shunt Clipper?
2. Types of Shunt Clippers
3. Implementation of shunt Clippers in Proteus ISIS.
4. Dual Clippers basics.
5. Implementation of Dual Clippers in Proteus ISIS.

So, let's get started:

What is a Shunt Clipper?

• In Shunt Clippers(Parallel Clippers), the diode is connected in Shunt(Parallel) to the input signal source & the load resistance, as shown in the below figure:
  

As the diode is in parallel with the load & source, so during the positive half cycle, the diode will be in the forward-biased state(short circuit) and thus no current will flow to the load resistance. While during the negative half cycle, the diode will be in a reverse-biased state(open circuit) and the load resistance will get all the current flow.

Now, let's have a look at the types of Shunt Clipper:

Types of Shunt Clippers

Shunt clippers are Classified into four main types, named:

• Positive
• Positive with bias
• Negative
• Negative with bias

Let's implement these Clipper types in the Proteus:

Implementation of Shunt Clippers in Proteus

So, open your Proteus software and add these components:

Components Required

1. Vsine
2. Diode
3. Resistor
4. Ground terminal
5. Oscilloscope

• We can get the first three components from the "Pick library" by searching for the required component.
• We can get the Ground Terminal by left-clicking on the screen and then go to Place>Terminal>Ground.
• Get the Oscilloscope from the "Virtual Instrument" in the leftmost bar.

Now let's design the first type of Shunt Clipper:

Positive Shunt Clipper:

Now place the above components in the Proteus workspace and design the circuit, as shown in the below figure:

As you can see in the above figure, the diode is placed parallel to the load resistance. The arrowhead of the diode points opposite to the input source. As we discussed above, the load resistance will get voltage only if the diode is in a reverse-biased state. In the current arrangement, during the negative cycle of the AC signal, the diode will be reverse-biased, and the load will get complete power. The positive cycle of the input will be clipped off, as the diode will be in a forward-biased state, not allowing any current to flow through the load.

Change the values of components according to the below table:

Components	Value
Resistor R1	600 ohm
Resistor R2	500 ohm
Vsine	Amplitude =110V,Frequency= 1000Hz
Oscilloscope	Time= 0.2m-1,Voltage 20V

• Now run the simulation and you will definitely acquire the required output:

Positive with bias:

If you recall from our previous lecture on Series Clippers, we have added a battery in the bias clippers. Here, we are going to do the same, as shown in the below figure:

As we can see in the above figure, a battery of 5V is added in series with the diode. By adding the battery in the circuit of positive shunt clippers, we can easily control the amount of signal to be clipped. This arrangement is called Positive Shunt Clippers with bias or Biased Positive Shunt Clippers.

In the above circuit, we placed the battery just after the diode and the Positive Terminal of the battery connects with the diode's arrowhead and the negative terminal is connected to the Vsine source.

Here's the output of Positive Bias Shunt Clipper:

Negative Shunt Clippers:

In negative Shunt Clippers, the diode polarity is reversed i.e.the positive end of the diode is connected to the negative terminal of the battery and the negative end of the diode is connected to the positive terminal of the battery, as shown in the below figure:

In this arrangement, the diode is forward-biased during the negative half cycle, so no current will pass to the load. We can say, the negative cycle is clipped off. While in the positive cycle, the diode is reversed bias(open circuit) and thus current is flowing through the load resistor.

We will get the following waveform on the oscilloscope:

Biased Negative Shunt Clippers:

By now, you must have understood that an extra battery is added in series with the diode to create a Bias Clipper. As it's a negative bias, so the polarity of the battery is reversed i.e. the negative terminal of the battery is connected to the diode and the positive terminal of the battery is connected to the Vsine Source. The output is shown in the below figure:

So, that was all about the Shunt Clippers. Now let's have a look at the third tye of clippers i.e. Dual Clippers. Let's get started:

What is a Dual Clipper?

As the name depicts, the Dual Clipper is a combination of two types of Shunt Clippers i.e.

1. Biased Shunt Positive Clipper.
2. Biased Shunt Negative Clipper.

Now, let's move towards its simulation:

Dual Clipper Proteus Simulation

We have studied both Positive & Negative Bias Shunt Clippers in the previous section, so now we need to add both clippers in a single circuit, as shown in the below figure:

As you can see in the above figure, the circuit has four parallel branches, let's discuss them one by one:

• The First branch has an AC input source.
• The second branch has a Biased Shunt Positive Clipper i.e. Diode and a battery.
• The third branch has a Biased Shunt Negative Clipper i.e. Diode and a battery, but here the polarity is reversed.
• In the fourth branch, we have the load.
• Pop the Play button, and have a look at the output:

One can see that we got a square wave that conducts the current in both directions but in clipped form. We need Dual clippers in the place where we need to clip some part of both sides of the sinusoidal wave.

So, that's all for today. In this article, we discussed what are Shunt Clippers? what are their types? and How to simulate in Proteus? We also discussed Dual Clippers along with their implementation in Proteus ISIS. Take care!!!

Full Wave Rectification in Proteus

Hey buddies, hope you all are fine. In our previous tutorial, we studied Half Wave Rectification and have seen that it rectifies the half wave of the AC signal. Today, we are going to study Full Wave Rectification to rectify the complete AC source. We will design the simulation of the Full Wave Rectifier in Proteus software. So, let's get started:

What is Full Wave Rectification?

A comprehensive definition of full-wave rectification is:

• Full-wave rectification is a process to convert both cycles(positive & negative) of input(sinusoidal) wave to pulsating DC (Direct current).

We have studied in the previous lecture that Half Wave Rectifiers are used to convert only one cycle(either positive or negative) of an AC signal into a DC signal, thus dissipating the 50% energy of the overall signal. But in Full Wave Rectifiers, both cycles of the AC signal are converted into a single pulsating DC signal.

We used a single diode in our circuit to achieve half-wave rectification but for full-wave rectification, we need to create a bridge using 4 diodes. Here's the circuit diagram of Full Wave Rectification, designed in Proteus:

Why Full Wave Rectification?

Full Wave Rectification is always preferred over half wave rectification because of following factors:

• In half-wave rectification, half of the wave gets wasted as the diode suppresses the second half cycle. But if we add the diode bridge, we can easily get the complete signal i.e. both of its cycles.
• Full Wave Rectification gives higher output values with a low ripple factor.

Full Wave Rectifier Simulation in Proteus ISIS:

You can download the complete Proteus Simulation of Full Wave Rectifier, by clicking the below button:

Full Wave Rectification in Proteus

First of all, we have to pick the components from the Proteus Components Library. We are going to need these three basic components:

1. Full Wave rectification bridge
2. Resistor
3. Alternating voltage source

• Go to the pick library button and select these components, as shown in the below figure:
  

• So, design the circuit for full-wave rectification in Proteus, as shown in the below figure:

• Change the value of load resistance to 500 ohms.
• Set the Vsine Frequency to 1000Hz & amplitude to 120V.
  

Now we are going to place an oscilloscope to monitor the input & output signals. You will find the oscilloscope in the "Virtual Instruments" section on the left bar. So, our final circuit with an oscilloscope is shown in the below figure:

• The oscilloscope settings are shown in the below figure:
  

The output of oscilloscope is shown in the below:

As you can see in the above figure:

• The Yellow(A Terminal) wave shows the sinusoidal wave. Whereas, the blue wave (B terminal) shows a positive half-cycle and the magenta one (C terminal) shows a negative half-cycle. And the magic is, both the outputs are direct currents and are combined in a single direction at the load resistance.

Thus, today we studied another simple Proteus experiment that shows what is full wave rectification, how to make the simplest circuit that shows the best output of full wave rectification and why we need the full wave rectification circuit. Till the next tutorial, take care!!!