3 Level Cascaded H Bridge Inverter
Hello friends! Today we will examine a cascaded H-bridge inverter in MATLAB and Simulink. We will begin with one bridge, work out its output states, and then see what changes when we connect bridge outputs in series and arrange three phases.
The historical project is titled “3 Level Cascaded H Bridge Inverter.” We will retain that title, but distinguish a bridge's three possible output levels from the number of phases and the larger set of levels available from a cascade. Those are different properties of a converter.
The original diagrams and scope images remain below so you can follow the model. They illustrate an older simulation environment. This revised explanation does not claim a fresh simulation run or treat a screenshot as proof of an inverter's efficiency or hardware readiness.
Start with One H-Bridge
An H-bridge contains two switching legs across a DC source. The load connects between the midpoints of those legs. Each midpoint can be connected toward the positive or negative rail, and the difference between the midpoint voltages determines the load voltage.
Let S1 and S2 be the upper and lower devices in the left leg, and S3 and S4 the upper and lower devices in the right leg. Define positive output as the left midpoint voltage minus the right midpoint voltage. Under ideal switching conditions, the useful states are:
| Conducting commanded devices | Ideal output | Meaning |
|---|---|---|
| S1 and S4 | +Vdc | Positive polarity |
| S2 and S3 | −Vdc | Negative polarity |
| S1 and S3 | 0 | Both midpoints at the positive rail |
| S2 and S4 | 0 | Both midpoints at the negative rail |
Thus, one full bridge can generate three output levels: −Vdc, zero and +Vdc. The two zero states have the same terminal voltage but may differ in current paths and device losses. With an inductive load, freewheeling paths must be considered as well as the commanded switch state.
Never command both devices in one leg on together. That can short the DC source through the switching devices. A logical switching table needs appropriate transition control and dead time before it becomes a practical gate-drive sequence.
What Cascading Adds
In a cascaded H-bridge converter, the AC outputs of multiple cells are connected in series. The phase voltage is the sum of their individual output voltages. This is an electrical series connection, not a Simulink block that merely adds two numerical signals.
For two equal cells with individual DC voltage E:
vphase = vcell1 + vcell2
Each cell can produce −E, zero or +E, so the combined available levels are −2E, −E, zero, +E and +2E. For N equal independently controlled cells, the usual maximum number of distinct phase levels is 2N + 1.
For example, two 100 V cells can provide phase levels of −200, −100, 0, 100 and 200 V. The same +100 V level can be made by setting the first cell to +100 V and the second to zero, or by exchanging their roles. These redundant combinations allow the controller to distribute cell usage.
The model overview below shows two bridge subsystems in each of three groups. Therefore, a fully used equal-source two-cell cascade is capable of five phase levels. If a particular command pattern only produces three, describe that as the selected operating sequence rather than claiming that two cascaded cells inherently have only three possible levels.
Likewise, three colored scope traces normally represent three phases or channels. They do not verify a three-level output. To count levels, inspect the distinct voltage plateaus of one named waveform over a suitable interval.
Follow the Historical Model
The lower subsystem supplies grouped control signals. Bus Selector blocks extract named signals and route them to the bridge subsystems. A bus is a structured collection of signals; it is not a power junction and does not combine DC-source energy.
The six bridge subsystems are arranged in three pairs. Voltage Measurement blocks feed direct waveform scopes and Fourier-analysis paths. Inspect each measurement's positive and negative terminals before naming its result a phase or line voltage.
Open one bridge subsystem and trace both the electrical terminals and control inputs separately. Record the DC source value, switch model, gate mapping, output polarity and any protective or parasitic elements. Repeating a mistaken cell six times only makes the resulting model harder to debug.
The internal diagram shows a DC source and four controlled devices arranged as a full bridge. Its two AC terminal labels identify the cell output. Check their polarity when connecting cells in series; reversing one cell changes whether its commanded voltage adds to or subtracts from the other cell.
Separate the DC Supplies Correctly
A conventional cascaded H-bridge needs suitable isolated or otherwise correctly arranged DC supplies for its cells. Connecting every source negative to one global ground can defeat the intended floating series connection and create unwanted current paths.
In simulation, ideal independent voltage sources make isolation easy to represent. In hardware, that isolation must come from an actual source or conversion arrangement. The absence of a wire in a drawing is not a specification for insulation, creepage or isolation rating.
The imperix cascaded H-bridge control note shows how practical converter control also has to consider cell voltages and power distribution. The series sum alone is only the beginning of the system design.
Understand the GTO Switch Model
The retained parameter window identifies a GTO thyristor model with an RC snubber. GTO means gate turn-off thyristor. It is not another name for a MOSFET, and ordinary transistors do not all remain latched on when their control signal is removed.
A physical GTO uses gate current for turn-on and a substantial negative gate-current drive for turn-off. A simplified simulator may represent those actions through a control signal and switching parameters. Do not copy a logic signal directly into a hardware gate-drive design.
The screenshot includes an on-state resistance, an inductance, a forward-voltage parameter and turn-off timing quantities. These belong to the model's behavior. Zero or very small values can produce an idealized result that omits important losses and transients.
The snubber parameters also need interpretation according to the selected block. The displayed infinite capacitance setting is a simulator parameter choice, not an instruction to buy an infinitely large capacitor. Consult the block documentation for the installed release before changing or reproducing these settings.
If you replace the GTO blocks with MOSFETs or IGBTs, review the switching commands, reverse-current paths, device parameters and timing. A replacement may be appropriate for another design, but it is not automatically equivalent just because the schematic symbol fits in the same position.
Build the Switching Sequence from a Clear Target
For a simple cell demonstration, first produce +E, zero and −E at a low fundamental frequency with a defined state order. Confirm the sign and magnitude at the cell's actual electrical terminals. Then add the second cell and verify the expected sums.
For a sinusoidal fundamental, modulation changes the dwell times of the available states. Carrier-based PWM, stepped switching and selective harmonic elimination are different choices, each with its own assumptions. The retained images do not expose enough pulse settings to prove a particular named modulation method.
With equal N-cell sources and ideal sinusoidal modulation in its linear range, a useful reference estimate is Vphase,1,peak ≈ ma × N × E, where ma is the modulation amplitude relative to the available stack voltage. The corresponding fundamental RMS value is the peak divided by √2.
For two 100 V cells and ma = 0.8, that estimate gives 160 V fundamental peak and about 113.1 V RMS. This is not the total RMS of the switched waveform, and it is not a result extracted from the historical screenshots.
Coordinate the Three Phases
Use three references displaced by 120 electrical degrees. For positive sequence, one common convention is sin(ωt), sin(ωt − 120 degrees) and sin(ωt + 120 degrees). At 50 Hz, the period is 20 ms, so 120 degrees corresponds to 6.667 ms.
Keep this fundamental displacement separate from any carrier phase shifts between cells. Phase-shifted carriers can distribute switching events, while the three fundamental references establish the output phase sequence. Those settings serve different purposes.
The line voltages are vAB = vA − vB, vBC = vB − vC and vCA = vC − vA. For balanced sinusoidal fundamentals, line RMS is √3 times phase-to-neutral RMS. Use consistent reference nodes, particularly when the load neutral floats.
What the Fourier Blocks Tell You
The historical Fourier block extracts a selected harmonic component using a window related to the configured fundamental frequency. Its magnitude and phase outputs describe that component; they do not mean the original switching waveform has physically become sinusoidal.
The surrounding model combines the extracted magnitude, phase and time in a mathematical function. Such a path can reconstruct a sinusoid representing the selected component. A smooth reconstruction is an analysis result, not the voltage available at the power terminals without filtering.
Set the analysis frequency to the actual fundamental. If the inverter runs at 50 Hz but the analyzer assumes 60 Hz, the window and phase estimate will not describe the intended periodic component correctly. Allow startup transients and the analysis window to settle before interpreting its output.
Check whether the selected block reports peak magnitude or RMS, and whether phase is expressed in degrees or radians. The current MathWorks Fourier Analysis documentation provides the definition for that block; an older block should be checked against its matching release documentation.
Interpret the Retained Output Plots
The direct waveform plot preserves the switching behavior of the displayed channels. Identify the measured terminals, vertical scale and time scale before comparing it with another scope. Similar shapes can have different amplitudes or represent different physical quantities.
A second direct scope may use another combination of phase or line measurements. Do not describe a waveform as “compressed” without checking axis scaling and measurement definitions. A plotting choice can change the appearance while leaving the underlying signal unchanged.
The analysis-related scope compares signals from the Fourier path and direct measurements. Separate the raw waveform, extracted magnitude and reconstructed fundamental in your notes. They answer different questions about the converter.
The other analysis scope provides another view of the same general process. A smooth curve can show the selected fundamental accurately while omitting all the switching harmonics. It cannot, by itself, establish low total harmonic distortion.
Calculate RMS and Harmonic Distortion
For sampled voltage values over a defined interval, total RMS is the square root of the mean of the squared samples. For a single ideal sinusoid, RMS is peak divided by √2. Apply the sinusoidal shortcut only to the sinusoidal component, not to an arbitrary staircase or PWM waveform.
As an example, if the fundamental is 100 V RMS, the third harmonic 8 V RMS and the fifth harmonic 6 V RMS, their combined harmonic magnitude is √(8² + 6²) = 10 V. The THD considering those harmonics is 10/100 × 100% = 10%.
The corresponding total RMS, ignoring DC and other harmonics, is √(100² + 8² + 6²), approximately 100.50 V. A total RMS reading close to 100 V therefore does not prove that the waveform is a pure sine wave.
State which harmonics and bandwidth are included. Use a steady interval containing an integer number of fundamental cycles when possible. Otherwise, windowing and spectral leakage need consideration before comparing numerical THD results.
Simulation Setup and Version Compatibility
The screenshots use the legacy Specialized Power Systems environment, including powergui. MathWorks documents the removal of that library starting with R2026a on its migration information page. A modern installation may therefore require converting the model rather than finding the same old blocks in the library browser.
For historical reproduction, use a compatible release and record its solver settings. For a rebuild in native Simscape Electrical, review component behavior, electrical references, solver configuration and measurement conversion. Do not assume that replacing each icon preserves every numerical assumption.
- Verify one bridge's three voltage states.
- Verify two series cells and their available sums.
- Check gate transitions and current paths.
- Add the three-phase references and confirm their sequence.
- Attach a clearly defined load and inspect current as well as voltage.
- Compare raw signals with Fourier-derived quantities.
- Repeat with a smaller simulation step to assess numerical sensitivity.
At a hypothetical 2 kHz switching frequency, one switching period is 500 microseconds. A 100-microsecond step gives only five steps per period and is a poor starting point for resolving detailed switching behavior. Choose the step from the events and quantities you need to capture, then check convergence rather than trusting a universal rule.
Test Cases That Reveal Model Errors
| Test | Expected useful observation |
|---|---|
| One cell positive and the other at zero | Stack output equals one cell voltage |
| Both cells positive | Stack output equals their sum |
| One positive and one negative with equal sources | Ideal net stack voltage is zero |
| All three phases given identical references | Ideal line differences collapse, revealing phase-command dependence |
| Small DC-source mismatch | Intermediate level spacing and cell power can become unequal |
| Inductive load added | Current phase and freewheeling behavior change |
Record the command state and measured voltage together. If a positive command produces a negative cell voltage, fix the polarity convention before compensating elsewhere with another minus sign. Consistent naming makes later control work substantially easier.
For a resistive load, instantaneous power is v²/R. For a general load, use v × i and average over the intended interval. A reactive load can return energy during part of a cycle, so instantaneous negative power does not automatically indicate a measurement fault.
Project Review and Further Study
The cascaded structure is modular and makes the relationship between cell voltage and output levels easy to study. Its practical challenges include DC-source arrangements, cell-power distribution, switching coordination and protection. More cells add available levels, but also add devices, drivers and measurements.
Read our Introduction to Multilevel Inverters for the broader topology comparison. The original project listing is retained for the historical resource; check its contents and release compatibility rather than relying on an old price or an assumed software version.
Frequently Asked Questions
Is a three-phase inverter the same as a three-level inverter?
No. Phase count describes coordinated AC outputs. Level count describes the distinct voltage values at a specified output point.
How many levels can two equal H-bridge cells produce?
Five at their series output when the available states are fully used: −2E, −E, zero, +E and +2E. A restricted modulation sequence may use fewer.
Does the Fourier block remove harmonics from the electrical output?
No. It analyzes the signal. A reconstructed fundamental is a mathematical result, while physical filtering requires an electrical filter or another suitable output arrangement.
Can I use these screenshots to build a high-power inverter?
They explain a simulation structure, not a complete hardware design. Gate-drive requirements, isolation, fault response, thermal limits and source behavior require separate engineering and verification.
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